公开(公告)号：US12259821B2

公开(公告)日：2025-03-25

申请号：US17310368

申请日：2020-01-29

Applicant: ARM LIMITED

Inventor： Simon John Craske ,  Jacob Eapen

IPC: G06F12/10 ,  G06F12/14

Abstract: There is provided an apparatus comprising input circuitry that receives requests comprising input addresses in an input domain. Output circuitry provides output addresses. The output addresses comprise secure physical addresses to secure storage circuitry and non-secure physical addresses to non-secure storage circuitry. Lookup circuitry stores a plurality of mappings comprising at least one mapping between the input addresses and the secure physical addresses, and at least one mapping between the input addresses and the non-secure physical addresses.

公开(公告)号：US11604854B2

公开(公告)日：2023-03-14

申请号：US16930650

申请日：2020-07-16

Applicant: Arm Limited

Inventor： Simon John Craske

IPC: G06F17/17 ,  G06F7/544

Abstract: A multiplier array for implementing a multiply-accumulate operation has a plurality of rows, where each row comprises multiplexer circuitry and adder circuitry, the multiplexer circuitry selecting, in dependence on a control input, one of a first multiplexer input value and a second multiplexer input value to provide as a first adder input value to the adder circuitry. In each row other than an initial row, the adder circuitry also receives as a second adder input value at least a portion of a result value produced in a preceding row. In a multiplication mode, the multiplier array implements the multiply-accumulate operation, and in a linear interpolation mode, the multiplier array implements a linear interpolation operation between a lower limit value and an upper limit value based on a weighting value.

公开(公告)号：US11579879B2

公开(公告)日：2023-02-14

申请号：US17224248

申请日：2021-04-07

Applicant: ARM LIMITED

Inventor： Max John Batley ,  Simon John Craske ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F12/1027

Abstract: An apparatus 2 has a processing pipeline 4 supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure 22, 30, 36, 50, 40, 64, 44 is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry 70 triggers a subset 102 of the entries of the storage structure to be placed in a power saving state.

公开(公告)号：US11461104B2

公开(公告)日：2022-10-04

申请号：US14952807

申请日：2015-11-25

Applicant: ARM LIMITED

Inventor： Michael John Williams ,  Richard Roy Grisenthwaite ,  Simon John Craske

IPC: G06F9/38 ,  G06F9/52 ,  G06F11/07

Abstract: Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.

公开(公告)号：US11307855B2

公开(公告)日：2022-04-19

申请号：US17096014

申请日：2020-11-12

Applicant: Arm Limited

Inventor： John Michael Horley ,  Simon John Craske

IPC: G06F9/30

Abstract: Instructions have an opcode and at least one data operand, the opcode identifying a data processing operation to perform on the at least one data operand. For a register-provided-opcode instruction specifying at least one source register, at least part of the opcode is a register-provided opcode represented by a first portion of data stored in said at least one source register of the register-provided-opcode instruction, and the at least one data operand comprises data represented by a second portion of the data stored in the at least one source register. The register-provided opcode is used to select between different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction.

公开(公告)号：US11216280B2

公开(公告)日：2022-01-04

申请号：US16695745

申请日：2019-11-26

Applicant: Arm Limited

Inventor： Simon John Craske

IPC: G06F9/38 ,  G06F9/30

Abstract: Exception control circuitry controls exception handling for processing circuitry. In response to an initial exception occurring when the processing circuitry is in a given exception level, the initial exception to be handled in a target exception level, the exception control circuitry stores exception control information to at least one exception control register associated with the target exception level, indicating at least one property of the initial exception or of processor state at a time the initial exception occurred. When at least one exception intercept configuration parameter stored in a configuration register indicates that exception interception is enabled, after storing the exception control information, and before the processing circuitry starts processing an exception handler for handling the initial exception in the target exception level, the exception control circuitry triggers a further exception to be handled in a predetermined exception level.

公开(公告)号：US11100010B2

公开(公告)日：2021-08-24

申请号：US16583539

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Simon John Craske

IPC: G06F12/14 ,  G06F12/02

Abstract: An apparatus and method are provided for performing data processing operations. The apparatus has processing circuitry for performing data processing operations configured to operate in a normal mode and a memory region management mode. A memory is used to store data accessed by the processing circuitry when performing the data processing operations. A memory region table is provided to define accessibility control information for each of a number of memory regions within the memory. An access control mechanism controls access to the memory in response to an access request issued by the processing circuitry, and a memory protection unit providing a bypass indication for one or more memory regions is referenced by the access control mechanism when the processing circuitry is in the memory region management mode. The access control mechanism is arranged to constrain access to the memory location identified by the access request based on the accessibility control information defined in the memory region management mode when the processing circuitry is operating in the normal mode. When the processing circuitry is operating in the memory region management mode, the access control mechanism is arranged to reference the memory protection unit and when the bypass indication is set for the memory region, to process the access to the memory location unconstrained by the memory region table.

公开(公告)号：US11080106B2

公开(公告)日：2021-08-03

申请号：US15066453

申请日：2016-03-10

Applicant: ARM LIMITED

Inventor： Michael John Williams ,  Simon John Craske

IPC: G06F9/54

Abstract: In an apparatus performing multi-threaded data processing event handling circuitry receives event information from the data processing circuitry indicative of an event which has occurred during the data processing operations. Visibility configuration storage holds a set of visibility configuration values, each visibility configuration value associated with a thread of the multiple threads and the event handling circuitry adapts its use of the event information to restrict visibility of the event information for software of threads other than the thread which generated the event information when a visibility configuration value for the thread which generated the event information has a predetermined value. This allows multi-threaded event monitoring to be supported, whilst protecting event information from a particular thread for which it is desired to limit its visibility to software of other threads.

公开(公告)号：US20210224071A1

公开(公告)日：2021-07-22

申请号：US17224248

申请日：2021-04-07

Applicant: ARM LIMITED

Inventor： Max John Batley ,  Simon John Craske ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296

Abstract: An apparatus 2 has a processing pipeline 4 supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure 22, 30, 36, 50, 40, 64, 44 is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry 70 triggers a subset 102 of the entries of the storage structure to be placed in a power saving state.

公开(公告)号：US11055440B2

公开(公告)日：2021-07-06

申请号：US16433296

申请日：2019-06-06

Applicant: ARM Limited

Inventor： Simon John Craske ,  Antony John Penton

IPC: G06F21/62 ,  G06F21/60 ,  G06F21/50 ,  G06F21/00 ,  G06F9/30 ,  G06F9/48 ,  G06F9/46 ,  G06F9/455 ,  G06F13/24

Abstract: A data processing apparatus has processing circuitry for executing first software at a first privilege level and second software at a second privilege level higher than the first privilege level. Attributes may be set by the first and second software to indicate whether execution of the data access instruction can be interrupted. For a predetermined type of data access instruction for which the second attribute set by the second software specifies that the instruction can be interrupted, the instruction may be set as interruptable even if the first attribute set by the first software specifies that the execution of the instruction cannot be interrupted.