公开(公告)号：US20240004653A1

公开(公告)日：2024-01-04

申请号：US17853613

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Laurent S. White ,  Shaizeen Aga

IPC: G06F9/30

CPC classification number: G06F9/3009 ,  G06F9/3004 ,  G06F9/30101

Abstract: An approach is provided for managing near-memory processing commands (“PIM commands”) from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command information to issue a PIM command sequence from a first processor thread, directed to a PIM-enabled memory element, while deferring the issuance of PIM command sequences from other processor threads, directed to the same PIM-enabled memory element. After the last PIM command in the PIM command sequence for the first processor thread has been issued, a PIM command sequence for another processor thread is issued, and so on. The approach allows multiple processor threads to concurrently issue fine grained PIM commands to the same PIM-enabled memory element without having to be aware of address-to-memory element mapping, and without having to coordinate with other threads.

公开(公告)号：US20230325317A1

公开(公告)日：2023-10-12

申请号：US17719225

申请日：2022-04-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Warren Boyer ,  Johnathan Alsop

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: Systems, apparatuses, and methods for reducing probe filter accesses in response to processing-in-memory (PIM) requests are disclosed. A coherent secondary unit receives PIM requests targeting a corresponding PIM device. For each PIM request that is received, the coherent secondary unit performs a lookup of a PIM address table (PAT). If the address of the PIM request matches an address of an existing entry in the PAT, the coherent secondary unit prevents the PIM request from being sent to a probe filter. Otherwise, if there is no match for the address of the PIM request in the entries of the PAT, the coherent secondary unit sends the PIM request to the probe filter, and the coherent secondary unit creates a new PAT entry for the address of the PIM request. Any subsequent PIM requests to the same address will match with the new entry in the PAT.

公开(公告)号：US20230266924A1

公开(公告)日：2023-08-24

申请号：US18311166

申请日：2023-05-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Shaizeen Dilawarhusen Aga

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.

公开(公告)号：US11656796B2

公开(公告)日：2023-05-23

申请号：US17219505

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Brandon K. Potter ,  Johnathan Alsop

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F3/0659 ,  G06F3/067 ,  G06F3/0658 ,  G06F9/30087 ,  G06F9/3838 ,  G06F3/0604

Abstract: A data processor includes a fabric-attached memory (FAM) interface for coupling to a data fabric and fulfilling memory access instructions. A requestor-side adaptive consistency controller coupled to the FAM interface requests notifications from a fabric manager for the fabric-attached memory regarding changes in requestors authorized to access a FAM region which the data processor is authorized to access. If a notification indicates that more than one requestor is authorized to access the FAM region, fences are activated for selected memory access instructions in a local application.

公开(公告)号：US20220317927A1

公开(公告)日：2022-10-06

申请号：US17219505

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Brandon K. Potter ,  Johnathan Alsop

IPC: G06F3/06 ,  G06F9/38 ,  G06F9/30

Abstract: A data processor includes a fabric-attached memory (FAM) interface for coupling to a data fabric and fulfilling memory access instructions. A requestor-side adaptive consistency controller coupled to the FAM interface requests notifications from a fabric manager for the fabric-attached memory regarding changes in requestors authorized to access a FAM region which the data processor is authorized to access. If a notification indicates that more than one requestor is authorized to access the FAM region, fences are activated for selected memory access instructions in a local application.

公开(公告)号：US20210389907A1

公开(公告)日：2021-12-16

申请号：US16900526

申请日：2020-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Shaizeen Dilawarhusen Aga

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.

公开(公告)号：US20210373805A1

公开(公告)日：2021-12-02

申请号：US16885677

申请日：2020-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F3/06

Abstract: An approach is provided for reducing command bus traffic between memory controllers and PIM-enabled memory modules using special PIM commands. The term “special PIM command” is used herein to describe embodiments and refers to a PIM command for which the corresponding module-specific command information is provided to memory modules via a non-command bus data path. A memory controller generates and issues a special PIM command to multiple PIM-enabled memory modules via a command bus and provides module-specific command information (e.g., address information) for the special PIM command to the PIM-enabled memory modules via the non-command bus data path that is shared by the PIM-enabled memory modules and the memory controller.