中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.018 seconds)

    Memory access commands with near-memory address generation
    2.
    发明授权
    Memory access commands with near-memory address generation 有权

    公开(公告)号：US11216373B2

    公开(公告)日：2022-01-04

    申请号：US16887713

    申请日：2020-05-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Johnathan Alsop

    IPC: G06F12/06 ,  G11C11/408

    Abstract: A memory controller may be configured with command logic that is capable of sending a memory access command having incomplete address information via a command/address bus that connects the memory controller to memory modules. The memory controller may send the memory access command via the bus for accessing data stored at memory locations of the memory modules. The memory locations may correspond to different near-memory generated reflecting that the data is not address aligned across the memory modules. Nonetheless, because of the near-memory address generation, the memory controller can send the memory access command having incomplete address information for accessing the data stored at the different addresses, as opposed to having to send multiple memory access commands specifying complete address information on the bus for accessing the data at the different addresses, thereby conserving usage of the available bus bandwidth, reducing power consumption, and increasing compute throughput.

    MEMORY ACCESS COMMANDS WITH NEAR-MEMORY ADDRESS GENERATION
    3.
    发明申请
    MEMORY ACCESS COMMANDS WITH NEAR-MEMORY ADDRESS GENERATION 有权

    公开(公告)号：US20210374055A1

    公开(公告)日：2021-12-02

    申请号：US16887713

    申请日：2020-05-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Johnathan Alsop

    IPC: G06F12/06 ,  G11C11/408

    Abstract: A memory controller may be configured with command logic that is capable of sending a memory access command having incomplete address information via a command/address bus that connects the memory controller to memory modules. The memory controller may send the memory access command via the bus for accessing data stored at memory locations of the memory modules. The memory locations may correspond to different near-memory generated reflecting that the data is not address aligned across the memory modules. Nonetheless, because of the near-memory address generation, the memory controller can send the memory access command having incomplete address information for accessing the data stored at the different addresses, as opposed to having to send multiple memory access commands specifying complete address information on the bus for accessing the data at the different addresses, thereby conserving usage of the available bus bandwidth, reducing power consumption, and increasing compute throughput.

    Dynamic multi-bank memory command coalescing
    4.
    发明授权
    Dynamic multi-bank memory command coalescing 有权

    公开(公告)号：US12254217B2

    公开(公告)日：2025-03-18

    申请号：US18311166

    申请日：2023-05-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Johnathan Alsop ,  Shaizeen Dilawarhusen Aga

    IPC: G06F3/06

    Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.

    DATA PLACEMENT WITH PACKET METADATA
    5.
    发明申请
    DATA PLACEMENT WITH PACKET METADATA 有权

    公开(公告)号：US20220197506A1

    公开(公告)日：2022-06-23

    申请号：US17124872

    申请日：2020-12-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sergey Blagodurov ,  Johnathan Alsop ,  SeyedMohammad SeyedzadehDelcheh

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Systems, apparatuses, and methods for determining data placement based on packet metadata are disclosed. A system includes a traffic analyzer that determines data placement across connected devices based on observed values of the metadata fields in actively exchanged packets across a plurality of protocol types. In one implementation, the protocol that is supported by the system is the compute express link (CXL) protocol. The traffic analyzer performs various actions in response to events observed in a packet stream that match items from a pre-configured list. Data movement is handled underneath the software applications by changing the virtual-to-physical address translation once the data movement is completed. After the data movement is finished, threads will pull in the new host physical address into their translation lookaside buffers (TLBs) via a page table walker or via an address translation service (ATS) request.

    Command throughput in PIM-enabled memory using available data bus bandwidth
    6.
    发明授权
    Command throughput in PIM-enabled memory using available data bus bandwidth 有权

    公开(公告)号：US11262949B2

    公开(公告)日：2022-03-01

    申请号：US16885677

    申请日：2020-05-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Johnathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

    IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00

    Abstract: An approach is provided for reducing command bus traffic between memory controllers and PIM-enabled memory modules using special PIM commands. The term “special PIM command” is used herein to describe embodiments and refers to a PIM command for which the corresponding module-specific command information is provided to memory modules via a non-command bus data path. A memory controller generates and issues a special PIM command to multiple PIM-enabled memory modules via a command bus and provides module-specific command information (e.g., address information) for the special PIM command to the PIM-enabled memory modules via the non-command bus data path that is shared by the PIM-enabled memory modules and the memory controller.

    APPROACH FOR PERFORMING EFFICIENT MEMORY OPERATIONS USING NEAR-MEMORY COMPUTE ELEMENTS
    9.
    发明公开
    APPROACH FOR PERFORMING EFFICIENT MEMORY OPERATIONS USING NEAR-MEMORY COMPUTE ELEMENTS 审中-公开

    公开(公告)号：US20230195618A1

    公开(公告)日：2023-06-22

    申请号：US17557568

    申请日：2021-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Shaizeen Aga ,  Johnathan Alsop ,  Nuwan Jayasena

    IPC: G06F12/06

    CPC classification number: G06F12/06

    Abstract: Near-memory compute elements perform memory operations and temporarily store at least a portion of address information for the memory operations in local storage. A broadcast memory command is then issued to the near-memory compute elements that causes the near-memory compute elements to perform a subsequent memory operation using their respective address information stored in the local storage. This allows a single broadcast memory command to be used to perform memory operations across multiple memory elements, such as DRAM banks, using bank-specific address information. In one implementation, the approach is used to process workloads with irregular updates to memory while consuming less command bus bandwidth than conventional approaches. Implementations include using conditional flags to selectively designate address information in local storage that is to be processed with the broadcast memory command.

    Memory request priority assignment techniques for parallel processors
    10.
    发明授权
    Memory request priority assignment techniques for parallel processors 有权

    公开(公告)号：US11507522B2

    公开(公告)日：2022-11-22

    申请号：US16706421

    申请日：2019-12-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sooraj Puthoor ,  Kishore Punniyamurthy ,  Onur Kayiran ,  Xianwei Zhang ,  Yasuko Eckert ,  Johnathan Alsop ,  Bradford Michael Beckmann

    IPC: G06F13/18 ,  G06F13/16

    Abstract: Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.

Patent Agency Ranking