公开(公告)号：US20250087621A1

公开(公告)日：2025-03-13

申请号：US18244205

申请日：2023-09-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Jing HSU ,  Hsu-Nan FANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: An interposer structure and a package structure are provided. The interposer structure includes a conductive portion, a dielectric layer, a plurality of first wires, and a plurality of second wires. The conductive portion has a first surface and a second surface opposite to the first surface. The dielectric layer encapsulates the conductive portion and exposes the first surface and the second surface. The first wires are formed on the first surface. The second wires are disposed over the second surface.

公开(公告)号：US20230144000A1

公开(公告)日：2023-05-11

申请号：US17522823

申请日：2021-11-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jun-Wei CHEN ,  Yu-Yuan YEH ,  Hsu-Nan FANG

IPC: H01L31/12 ,  H01L31/02

CPC classification number: H01L31/12 ,  H01L31/02005

Abstract: An electronic package is provided. The electronic package includes a carrier, a first electronic component, a bonding element, and a barrier. The carrier has a conductive layer. The first electronic component is disposed adjacent to the carrier and has a first terminal and a second terminal. The bonding element is configured to electrically connect the conductive layer to the first terminal. The barrier is configured to avoid electrically bypassing an electrical path in the first electronic component and between the first terminal and the second terminal.

公开(公告)号：US20220415799A1

公开(公告)日：2022-12-29

申请号：US17356199

申请日：2021-06-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG

IPC: H01L23/535 ,  H01L25/16 ,  H01L23/00

Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes an electronic component having a first surface, a second surface opposite to the first surface and a circuit structure closer to the first surface than to the second surface. The semiconductor package structure also includes a passive component connected to the second surface of the electronic component. The semiconductor package structure further includes a conductive element extending into the electronic component and configured to electrically connect the circuit structure with the passive component.

公开(公告)号：US20220367369A1

公开(公告)日：2022-11-17

申请号：US17879677

申请日：2022-08-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/304 ,  H01L21/768 ,  H01L21/56

Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.

公开(公告)号：US20210366864A1

公开(公告)日：2021-11-25

申请号：US16882253

申请日：2020-05-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG

IPC: H01L23/00

Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first wiring structure and at least one electronic device. The at least one electronic device is connected to the first wiring structure through at least two joint structures. The at least two joint structures respectively include different materials.

公开(公告)号：US20210225737A1

公开(公告)日：2021-07-22

申请号：US16748566

申请日：2020-01-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first semiconductor element, a first redistribution layer, a second redistribution layer, and a conductive via. The first semiconductor element has a first active surface and a first back surface opposite to the first active surface. The first redistribution layer is disposed adjacent to the first back surface of the first semiconductor element. The second redistribution layer is disposed adjacent to the first active surface of the first semiconductor element. The conductive via is disposed between the first redistribution layer and the second redistribution layer, where the conductive via inclines inwardly from the second redistribution layer to the first redistribution layer.

公开(公告)号：US20210175163A1

公开(公告)日：2021-06-10

申请号：US16703454

申请日：2019-12-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor device package includes a redistribution structure, a conductive substrate stacked on the redistribution structure and an encapsulant encapsulating the redistribution structure and the conductive substrate. The encapsulant encapsulates a side surface of the conductive substrate. A method for manufacturing an electronic device package includes: providing a carrier, forming a redistribution structure on the carrier, mounting a conductive substrate on a first surface of the redistribution structure, forming a first encapsulant to encapsulate the first surface of the redistribution structure and a side surface of the conductive substrate, and removing the carrier.

公开(公告)号：US20210134711A1

公开(公告)日：2021-05-06

申请号：US16676280

申请日：2019-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/463 ,  H01L21/48

Abstract: A package structure includes at least one electronic device, a protection layer and an encapsulant. The electronic device has a first surface and includes a plurality of bumps disposed adjacent to the first surface thereof. Each of the bumps has a first surface. The protection layer covers the bumps and the first surface of the electronic device, and has a first surface. The encapsulant covers the protection layer and at least a portion of the electronic device, and has a first surface. The first surfaces of the bumps, the first surface of the protection layer and the first surface of the encapsulant are substantially coplanar with each other.

公开(公告)号：US20210091042A1

公开(公告)日：2021-03-25

申请号：US16581009

申请日：2019-09-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/56

Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.

公开(公告)号：US20210082853A1

公开(公告)日：2021-03-18

申请号：US16573672

申请日：2019-09-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Sheng LIN ,  Chin-Li KAO ,  Hsu-Nan FANG

IPC: H01L23/00

Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.