公开(公告)号：US20210193578A1

公开(公告)日：2021-06-24

申请号：US16721664

申请日：2019-12-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L21/304

Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.

公开(公告)号：US20230223352A1

公开(公告)日：2023-07-13

申请号：US18121569

申请日：2023-03-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/31 ,  H01L23/18 ,  H01L27/148 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L21/56 ,  H01L23/18 ,  H01L23/3114 ,  H01L24/05 ,  H01L27/148 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2924/181

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

公开(公告)号：US20210159156A1

公开(公告)日：2021-05-27

申请号：US16691296

申请日：2019-11-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG ,  Chen Yuan WENG

IPC: H01L23/498 ,  H01L23/544 ,  H01L23/528

Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.

公开(公告)号：US20180061805A1

公开(公告)日：2018-03-01

申请号：US15683697

申请日：2017-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.

公开(公告)号：US20220367369A1

公开(公告)日：2022-11-17

申请号：US17879677

申请日：2022-08-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/304 ,  H01L21/768 ,  H01L21/56

Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.

公开(公告)号：US20210091042A1

公开(公告)日：2021-03-25

申请号：US16581009

申请日：2019-09-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/56

Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.

公开(公告)号：US20200381359A1

公开(公告)日：2020-12-03

申请号：US16430365

申请日：2019-06-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Jun ZHUANG ,  Hsu-Nan FANG

IPC: H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution layer (RDL) structure, a first die, a molding compound and an interconnect structure. The first die is disposed on the RDL structure. The molding compound is disposed on the RDL structure. The interconnect structure electrically connects the first die to the RDL structure.

公开(公告)号：US20210327819A1

公开(公告)日：2021-10-21

申请号：US16852259

申请日：2020-04-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/31 ,  H01L23/18 ,  H01L27/148 ,  H01L23/00

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

公开(公告)号：US20180061815A1

公开(公告)日：2018-03-01

申请号：US15680063

申请日：2017-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan FANG ,  Chun-Jun ZHUANG

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/04 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/02311 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package device comprises a circuit layer, an electronic component disposed on the circuit layer, a package element and a first encapsulant. The package element is disposed on the circuit layer. The package element includes at least two electrical contacts electrically connected to the circuit layer. The first encapsulant is disposed on the circuit layer. The first encapsulant encapsulates the electronic component and the package element and exposes the electrical contacts of the package element.

公开(公告)号：US20170256508A1

公开(公告)日：2017-09-07

申请号：US15057673

申请日：2016-03-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Jun ZHUANG ,  Hung-Chun KUO ,  Chun-Chin HUANG

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/03472 ,  H01L2224/06051 ,  H01L2224/06152 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/14136 ,  H01L2224/14151 ,  H01L2224/14156 ,  H01L2224/17106 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81447 ,  H01L2924/15321 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device includes a substrate main body, a plurality of first bump pads, and redistribution layer (RDL). The first bump pads are disposed adjacent to a surface of the substrate main body, each of the first bump pads has a first profile from a top view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile. The RDL is disposed adjacent to the surface of the substrate main body, and the RDL includes a first portion disposed between two first bump pads.