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    PHOTODIODE ARRAY AND METHOD FOR MANUFACTURING PHOTODIODE ARRAY
    1.
    发明公开
    PHOTODIODE ARRAY AND METHOD FOR MANUFACTURING PHOTODIODE ARRAY 审中-公开

    公开(公告)号：US20240347504A1

    公开(公告)日：2024-10-17

    申请号：US18292529

    申请日：2022-07-20

    Applicant: KYOCERA Corporation

    Inventor： Genshitaro KAWAMURA ,  Naoyoshi KOMATSU

    IPC: H01L25/04 ,  H01L31/02 ,  H01L31/0296 ,  H01L31/105

    CPC classification number: H01L25/042 ,  H01L31/02005 ,  H01L31/0296 ,  H01L31/105

    Abstract: A PIN semiconductor layer including Mg2Si, a first electrode connected to a first surface of the PIN semiconductor layer, a support member being in contact with a surface of the first electrode via a connection layer, a second electrode and a third electrode which are connected to the PIN semiconductor layer on a second surface opposite to the first surface of the PIN semiconductor layer, and an ROIC structure connected to the second electrode and the third electrode are provided. The first electrode is disposed around a through groove, the second electrode is connected to a portion of the second surface where a p+ type semiconductor layer is located, the third electrode is connected to the first electrode and the through groove, the support member comprises a light-transmissive member having a lower coefficient of thermal expansion than Mg2Si, and the connection layer includes an opening portion.

    Wiring board, electronic component package, and electronic apparatus
    3.
    发明授权
    Wiring board, electronic component package, and electronic apparatus 有权

    公开(公告)号：US12068420B2

    公开(公告)日：2024-08-20

    申请号：US17436111

    申请日：2020-03-09

    Applicant: KYOCERA Corporation

    Inventor： Toshihiko Kitamura

    IPC: H01L31/02 ,  H01L31/0203 ,  H01S5/02315

    CPC classification number: H01L31/02005 ,  H01L31/0203 ,  H01S5/02315

    Abstract: A dielectric substrate has a first surface including a first terminal connector and a second terminal connector located along a first side surface. A recess is between the first terminal connector and the second terminal connector. The recess has a first inner surface continuous with the first terminal connector, a second inner surface continuous with the second terminal connector, and a bottom surface between the first inner surface and the second inner surface. The first terminal connector has first wettability with a bond on its surface, and a first region has second wettability with the bond on its surface lower than the first wettability.

    Semiconductor die and photoelectric device integrated in same package
    4.
    发明授权
    Semiconductor die and photoelectric device integrated in same package 有权

    公开(公告)号：US12021069B2

    公开(公告)日：2024-06-25

    申请号：US17081783

    申请日：2020-10-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Jen-Yuan Chang ,  Chia-Ping Lai

    IPC: H01L25/16 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/0232 ,  H01L31/18

    CPC classification number: H01L25/167 ,  H01L31/02005 ,  H01L31/02164 ,  H01L31/02327 ,  H01L31/18

    Abstract: The semiconductor structure includes a die, a dielectric layer surrounding the die, a photoelectric device disposed adjacent to the die and surrounded by the dielectric layer, a first opening extending through the redistribution layer and configured to receive a light-conducting member, and a dielectric liner extending at least partially through the redistribution layer and surrounding the first opening. A method for forming a semiconductor structure includes forming a dielectric layer to surround a die; and disposing a photoelectric device surrounded by the dielectric layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; forming a recess over the photoelectric device; disposing a dielectric material into the recess; removing a portion of the dielectric material to form a dielectric liner and a first opening over the photoelectric device. The dielectric liner extends at least partially through the redistribution layer and surrounding the first opening.

    SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS
    6.
    发明公开
    SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS 审中-公开

    公开(公告)号：US20240194660A1

    公开(公告)日：2024-06-13

    申请号：US18587461

    申请日：2024-02-26

    Applicant: ROHM CO., LTD.

    Inventor： Yoshizo OSUMI ,  Taro NISHIOKA ,  Hiroaki MATSUBARA

    IPC: H01L25/16 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/18 ,  H01L33/56 ,  H01L33/62

    CPC classification number: H01L25/167 ,  H01L31/02005 ,  H01L31/0203 ,  H01L33/56 ,  H01L33/62 ,  H01L31/18 ,  H01L2933/005 ,  H01L2933/0066

    Abstract: Semiconductor device includes first lead, second lead, light-emitting element, light-receiving element, transparent resin and first resin. First lead includes first die pad having first obverse surface and first reverse surface mutually opposite in thickness direction. Second lead includes second die pad having second obverse surface facing same side as first obverse surface in thickness direction and second reverse surface facing same side as first reverse surface in thickness direction. Light-emitting element is mounted on first obverse surface. Light-receiving element is mounted on second obverse surface. Transparent resin covers portions of light-emitting element and light-receiving element. First resin covers transparent resin. Transparent resin includes transparent-resin obverse surface facing same side as first obverse surface in thickness direction, and transparent-resin reverse surface facing same side as first reverse surface in thickness direction. Transparent-resin reverse surface has surface roughness larger than that of transparent-resin obverse surface.

    Embedded wafer level optical sensor packaging
    7.
    发明授权
    Embedded wafer level optical sensor packaging 有权

    公开(公告)号：US12002898B2

    公开(公告)日：2024-06-04

    申请号：US17344520

    申请日：2021-06-10

    Applicant: STMICROELECTRONICS PTE LTD

    Inventor： Jing-En Luan

    IPC: H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/18

    CPC classification number: H01L31/12 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/186

    Abstract: The present disclosure is directed to a sensor die with an embedded light sensor and an embedded light emitter as well as methods of manufacturing the same. The light emitter in the senor die is surrounded by a resin. The sensor die is incorporated into semiconductor device packages as well as methods of manufacturing the same. The semiconductor device packages include a first optically transmissive structure on the light sensor of the sensor die and a second optically transmissive structure on the light emitter of the sensor die. The first optically transmissive structure and the second optically transmissive structure cover and protect the light sensor and the light emitter, respectively. A molding compound is on a surface of a sensor die and covers sidewalls of the first and second optically transmissive structures on the sensor die.

    ELECTROMAGNETIC WAVE DETECTOR AND ELECTROMAGNETIC WAVE DETECTOR ARRAY
    8.
    发明公开
    ELECTROMAGNETIC WAVE DETECTOR AND ELECTROMAGNETIC WAVE DETECTOR ARRAY 审中-公开

    公开(公告)号：US20240154046A1

    公开(公告)日：2024-05-09

    申请号：US18280674

    申请日：2021-03-30

    Applicant: Mitsubishi Electric Corporation

    Inventor： Satoshi OKUDA ,  Shimpei OGAWA ,  Shoichiro FUKUSHIMA ,  Masaaki SHIMATANI

    IPC: H01L31/02 ,  H01L31/0224 ,  H01L31/0352

    CPC classification number: H01L31/02005 ,  H01L31/022408 ,  H01L31/035272

    Abstract: An electromagnetic wave detector includes a semiconductor layer, an insulating layer disposed on the semiconductor layer and having an opening, a two-dimensional material layer extending from on the opening to on the insulating layer, including a connection part in contact with a peripheral part of the insulating layer facing the opening, and electrically connected to the semiconductor layer, a first electrode part disposed on the insulating layer and electrically connected to the two-dimensional material layer, a second electrode part electrically connected to the semiconductor layer, and a unipolar barrier layer disposed between the semiconductor layer and the connection part of the two-dimensional material layer and electrically connected to each of the semiconductor layer and the two-dimensional material layer.

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