公开(公告)号：US20210295593A1

公开(公告)日：2021-09-23

申请号：US17338846

申请日：2021-06-04

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Karl D. Mann ,  Tyson J. Bergland ,  Winnie W. Yeung

IPC: G06T15/80 ,  G06T15/00 ,  G06T15/04 ,  G09G5/36

Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.

公开(公告)号：US20190266102A1

公开(公告)日：2019-08-29

申请号：US16410828

申请日：2019-05-13

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Kenneth C. Dyke ,  Karthik Ramani ,  Winnie W. Yeung ,  Anthony P. DeLaurier ,  Luc R. Semeria ,  David A. Gotwalt ,  Srinivasa Rangan Sridharan ,  Muditha Kanchana

IPC: G06F12/123 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0808

Abstract: Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.

公开(公告)号：US09761303B2

公开(公告)日：2017-09-12

申请号：US15009200

申请日：2016-01-28

Applicant: Apple Inc.

Inventor： Abdulkadir U. Diril ,  Adam T. Moerschell ,  Anthony P. DeLaurier

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C19/00

Abstract: Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to different schemes. This technique may be pertinent to a storage element that has a portion for which the associated bit values do not change frequently relative to another portion of the storage element. For such a storage element, a high-frequency portion may be clocked upon an access to the storage element, while a low-frequency portion may be clocked only if there is a change in the associated bit values. This technique can be applied to various storage elements, including registers and FIFO buffer entries. An apparatus may be designed such that the low-frequency and high-frequency portions of a storage element do not change during operation. Alternatively, the low-frequency and high-frequency portions of the storage element may be changeable based on a current operating mode of the apparatus.