公开(公告)号：US20250103501A1

公开(公告)日：2025-03-27

申请号：US18795416

申请日：2024-08-06

Applicant: Apple Inc.

Inventor： Mladen Wilder ,  Karthik Ramani ,  Tyson J. Bergland

IPC: G06F12/084 ,  G06F12/0817 ,  G06F12/0837

Abstract: Techniques are disclosed relating to data compression in graphics processors. In some embodiments, first and second graphics processor cores include respective shader processor circuitry configured to execute graphics shader programs. Cache circuitry may be configured to store surface data, including a compressed block of surface data and metadata for the compressed block of surface data. Lock control circuitry may lock metadata for the second graphics processor core for the compressed block of surface data based on an access to the metadata by the first graphics processor core and prevent read accesses to the compressed block by the second graphics processor core until the lock on the metadata is released. This may provide consistency across graphics cores for compressed data.

公开(公告)号：US20210295593A1

公开(公告)日：2021-09-23

申请号：US17338846

申请日：2021-06-04

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Karl D. Mann ,  Tyson J. Bergland ,  Winnie W. Yeung

IPC: G06T15/80 ,  G06T15/00 ,  G06T15/04 ,  G09G5/36

Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.

公开(公告)号：US10255655B1

公开(公告)日：2019-04-09

申请号：US15625723

申请日：2017-06-16

Applicant: Apple Inc.

Inventor： Tyson J. Bergland ,  Abdulkadir U. Diril ,  Anthony P. Delaurier

IPC: G06T1/60 ,  G06T1/20 ,  G06T11/00 ,  G06F17/50

Abstract: Techniques relating to serial processing of pixels in a texture processing pipeline. In some embodiments, the pipeline receives pixel data for a set of pixels in parallel but processes the pixels in the set serially in a pipelined fashion. In some embodiments, the pipeline includes a stage configured to retain texel data for use by a subsequently processed pixel. They may allow overlapping texels to be fetched once for the set of pixels rather than multiple times for different pixels in the set. In some embodiments, the pipeline uses a selected ordering of serial processing for the pixels, where the ordering increases the potential for texel overlap, relative to one or more other orderings.

公开(公告)号：US20220377352A1

公开(公告)日：2022-11-24

申请号：US17816136

申请日：2022-07-29

Applicant: Apple Inc.

Inventor： Tyson J. Bergland ,  Anthony P. DeLaurier ,  Karthik Ramani ,  Stephan Lachowsky

IPC: H04N19/182 ,  H03M7/30

Abstract: Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, amounts of data needed to represent, using a given lossless compression technique of the multiple lossless compression techniques, individual pixels in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on comparison, among the compression techniques, of sums of: the determined amount of data for an individual pixel for a given lossless compression technique and compression metadata size for a given lossless compression technique. The compression circuitry may generate and store information that encodes values for the set of pixels using the selected compression technique.

公开(公告)号：US11405622B2

公开(公告)日：2022-08-02

申请号：US16855459

申请日：2020-04-22

Applicant: Apple Inc.

Inventor： Tyson J. Bergland ,  Anthony P. DeLaurier ,  Karthik Ramani ,  Stephan Lachowsky

IPC: H04N11/02 ,  H04N19/182 ,  H03M7/30

Abstract: Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, a number of bits needed to represent a least compressible pixel, using that technique, in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on the determined numbers of bits for the multiple compression techniques and corresponding header sizes. In some embodiments, the compression circuitry determines, for multiple regions of pixels in the set of pixels, for ones of the compression techniques, a region number of bits needed to represent a least compressible pixel, using that technique. The selection of a compression technique may be further based on region numbers of bits.

公开(公告)号：US20210337218A1

公开(公告)日：2021-10-28

申请号：US16855459

申请日：2020-04-22

Applicant: Apple Inc.

Inventor： Tyson J. Bergland ,  Anthony P. DeLaurier ,  Karthik Ramani ,  Stephan Lachowsky

IPC: H04N19/182 ,  H03M7/30

Abstract: Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, a number of bits needed to represent a least compressible pixel, using that technique, in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on the determined numbers of bits for the multiple compression techniques and corresponding header sizes. In some embodiments, the compression circuitry determines, for multiple regions of pixels in the set of pixels, for ones of the compression techniques, a region number of bits needed to represent a least compressible pixel, using that technique. The selection of a compression technique may be further based on region numbers of bits.

公开(公告)号：US20210074053A1

公开(公告)日：2021-03-11

申请号：US16953021

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Michael J. Swift ,  Michal Valient ,  Robert S. Hartog ,  Tyson J. Bergland ,  Gokhan Avkarogullari

IPC: G06T15/04 ,  G06T1/60 ,  G06F9/38 ,  G06T11/00 ,  G06F12/1009 ,  G06F9/50 ,  G06T15/00 ,  G06F12/0811

Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

公开(公告)号：US20240429938A1

公开(公告)日：2024-12-26

申请号：US18755302

申请日：2024-06-26

Applicant: Apple Inc.

Inventor： Tyson J. Bergland ,  Karthik Ramani ,  Stephan Lachowsky ,  Justin A. Hensley ,  Davoud A. Jamshidi

IPC: H03M7/30 ,  H04N19/176 ,  H04N19/182

Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.

公开(公告)号：US20210336632A1

公开(公告)日：2021-10-28

申请号：US16855540

申请日：2020-04-22

Applicant: Apple Inc.

Inventor： Tyson J. Bergland ,  Karthik Ramani ,  Stephan Lachowsky ,  Justin A. Hensley ,  Davoud A. Jamshidi

IPC: H03M7/30 ,  H04N19/176 ,  H04N19/182

Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.

公开(公告)号：US20210134052A1

公开(公告)日：2021-05-06

申请号：US16673883

申请日：2019-11-04

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Karl D. Mann ,  Tyson J. Bergland ,  Winnie W. Yeung

IPC: G06T15/80 ,  G06T15/00 ,  G06T15/04 ,  G09G5/36

Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry. In some embodiments, write circuitry is configured to write the first and second compressed blocks of pixel data in a combined write to a higher level in the storage hierarchy.