公开(公告)号：US20180121199A1

公开(公告)日：2018-05-03

申请号：US15629126

申请日：2017-06-21

Applicant: Apple Inc.

Inventor： Tal Uliel ,  Jeffry E. Gonion ,  Ali Sazegari ,  Eric Bainville

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/485 ,  G06F7/487 ,  G06F7/544

CPC classification number: G06F9/30036 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/5443 ,  G06F9/30014

Abstract: In an embodiment, a processor may implement a fused multiply-add (FMA) instruction that accepts vector operands having vector elements with a first precision, and performing both the multiply and add operations at a higher precision. The add portion of the operation may add adjacent pairs of multiplication results from the multiply portion of the operation, which may allow the result to be stored in a vector register of the same overall length as the input vector registers but with fewer, higher precision vector elements, in an embodiment. Additionally, the overall operation may have high accuracy because of the higher precision throughout the operation.

公开(公告)号：US20170357894A1

公开(公告)日：2017-12-14

申请号：US15619348

申请日：2017-06-09

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Ali Sazegari

IPC: G06N3/08 ,  G06F3/06

CPC classification number: G06N3/063 ,  G06F17/153 ,  G06N3/0454

Abstract: Convolution processing performance in digital image processing is enhanced using a data packing process for convolutional layers in deep neural networks and corresponding computation kernel code. The data packing process includes an input and weight packing of the input channels of data into a contiguous block of memory in preparation for convolution. In addition, data packing process includes an output unpacking process for unpacking convolved data into output channel blocks of memory, where the input channel block and output channel block sizes are configured for efficient data transfer and data reuse during convolution. The input packing and output packing processes advantageously improve convolution performance and conserve power while satisfying the real-time demands of digital image processing.

公开(公告)号：US20170090902A1

公开(公告)日：2017-03-30

申请号：US14941229

申请日：2015-11-13

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Ali Sazegari

IPC: G06F9/445

Abstract: A novel software updating method is provided. A target file is divided into segments, where some segments are updated by patching, while other segments are updated by archiving. The segmentation of the update allows very large files such as DYLD shared caches to be patched in-place, i.e., by using free space available within the file to perform patching rather than requiring enough free space on disk to store both the new version and the old version of the file. The segmentation of the update also allows each segment to be updated individually by the most optimal update method (copy, patch, or archive) so that the size of the update file can be minimized.

公开(公告)号：US11914983B2

公开(公告)日：2024-02-27

申请号：US17898013

申请日：2022-08-29

Applicant: Apple Inc.

Inventor： Christian T. Martelock ,  Ali Sazegari ,  Eric Bainville

IPC: G06F8/61 ,  G06F8/658 ,  G06F9/445

CPC classification number: G06F8/63 ,  G06F8/658 ,  G06F9/44505

Abstract: Aspects and features include using a virtual disk image to improve computational performance when applying a software patch. Compressed extents within a stored disk image are detected. The compressed extents are virtually reordered to form compressed forks within a virtual disk image and the compressed forks are selected for decompression based on code to be patched. A decompressed fork with the patch is virtually written to the same or another virtual disk image as an updated fork, and the virtual disk image is used to write to storage, either to overwrite the same stored disk image or to produce an updated, compressed disk image. In some examples, the virtual disk image is validated prior to writing to the compressed image by comparing an output hash from the compressed disk image with a known hash to validate the virtual disk image.

公开(公告)号：US20200241876A1

公开(公告)日：2020-07-30

申请号：US16847068

申请日：2020-04-13

Applicant: Apple Inc.

Inventor： O-Cheng Chang ,  Tal Uliel ,  Eric Bainville ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F9/38

Abstract: In an embodiment, a processor (e.g. a CPU) may offload transcendental computation to a computation engine that may efficiently perform transcendental functions. The computation engine may implement a range instruction that may be included in a program being executed by the CPU. The CPU may dispatch the range instruction to the computation engine. The range instruction may take an input operand (that is to be evaluated in a transcendental function, for example) and may reference a range table that defines a set of ranges for the transcendental function. The range instruction may identify one of the set of ranges that includes the input operand. For example, the range instruction may output an interval number identifying which interval of an overall set of valid input values contains the input operand. In an embodiment, the range instruction may take an input vector operand and output a vector of interval identifiers.

公开(公告)号：US20200225958A1

公开(公告)日：2020-07-16

申请号：US16837631

申请日：2020-04-01

Applicant: Apple Inc.

Inventor： Tal Uliel ,  Eric Bainville ,  Jeffry E. Gonion ,  Ali Sazegari, PhD

IPC: G06F9/38

Abstract: In an embodiment, a computation engine may perform dot product computations on input vectors. The dot product operation may have a first operand and a second operand, and the dot product may be performed on a subset of the vector elements in the first operand and each of the vector elements in the second operand. The subset of vector elements may be separated in the first operand by a stride that skips one or more elements between each element to which the dot product operation is applied. More particularly, in an embodiment, the input operands of the dot product operation may be a first vector having second vectors as elements, and the stride may select a specified element of each second vector.

公开(公告)号：US20200034145A1

公开(公告)日：2020-01-30

申请号：US16043772

申请日：2018-07-24

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Jeffry E. Gonion ,  Ali Sazegari ,  Gerard R. Williams, III

IPC: G06F9/30 ,  G06F17/16

Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.

公开(公告)号：US20190250917A1

公开(公告)日：2019-08-15

申请号：US15896582

申请日：2018-02-14

Applicant: Apple Inc.

Inventor： O-Cheng Chang ,  Tal Uliel ,  Eric Bainville ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30076 ,  G06F9/3004 ,  G06F9/3802

Abstract: In an embodiment, a computation engine may offload a processor (e.g. a CPU) and efficiently perform transcendental functions. The computation engine may implement a range instruction that may be included in a program being executed by the CPU. The CPU may dispatch the range instruction to the computation engine. The range instruction may take an input operand (that is to be evaluated in a transcendental function, for example) and may reference a range table that defines a set of ranges for the transcendental function. The range instruction may identify one of the set of ranges that includes the input operand. For example, the range instruction may output an interval number identifying which interval of an overall set of valid input values contains the input operand. In an embodiment, the range instruction may take an input vector operand and output a vector of interval identifiers.

公开(公告)号：US10346163B2

公开(公告)日：2019-07-09

申请号：US15800342

申请日：2017-11-01

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US20180365007A1

公开(公告)日：2018-12-20

申请号：US15955417

申请日：2018-04-17

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Ali Sazegari

IPC: G06F8/71 ,  G06F8/65 ,  G06F8/658

Abstract: A novel software updating method is provided. A target file is divided into segments, where some segments are updated by patching, while other segments are updated by archiving. The segmentation of the update allows very large files such as DYLD shared caches to be patched in-place, i.e., by using free space available within the file to perform patching rather than requiring enough free space on disk to store both the new version and the old version of the file. The segmentation of the update also allows each segment to be updated individually by the most optimal update method (copy, patch, or archive) so that the size of the update file can be minimized.