公开(公告)号：US20150058572A1

公开(公告)日：2015-02-26

申请号：US13971800

申请日：2013-08-20

Applicant: Apple Inc.

Inventor： Timothy A. Olson ,  Terence M. Potter ,  James S. Blomgren ,  Andrew M. Havlir

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06T1/20 ,  Y02D10/13

Abstract: Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may store a subset of operands, and may use less power and have quicker access times than the register file. In some embodiments, intelligent operand prefetching may speed execution by reducing memory bank conflicts (e.g., conflicts within a register file containing multiple memory banks). An unused operand slot for another instruction (e.g., an instruction that does not require a maximum number of source operands allowed by an instruction set architecture) may be used to prefetch an operand for another instruction in one embodiment. Prefetched operands may be stored in an operand cache, and prefetching may occur based on software-provided information.

Abstract translation: 指令可能需要执行一个或多个操作数，这可以从寄存器文件提供。 然而，在GPU的上下文中，寄存器文件可以是相对较大的结构，并且从寄存器文件的读取可能是能量和/或时间密集的。操作数高速缓存可以存储操作数的子集，并且可以使用更少的功率并具有 比寄存器文件更快的访问时间。 在一些实施例中，智能操作数预取可以通过减少存储体冲突（例如，包含多个存储体的寄存器文件内的冲突）来加速执行。 在一个实施例中，用于另一指令的未用操作数时隙（例如，不需要由指令集体系结构允许的最大数量的源操作数的指令）可用于预取另一指令的操作数。 预取操作数可以存储在操作数缓存中，并且可以基于软件提供的信息进行预取。

公开(公告)号：US20150058389A1

公开(公告)日：2015-02-26

申请号：US13971753

申请日：2013-08-20

Applicant: Apple Inc.

Inventor： James S. Blomgren ,  Terence M. Potter

IPC: G06F17/10

CPC classification number: G06F7/525

Abstract: Techniques are disclosed relating to performing extended multiplies without a carry flag. In one embodiment, an apparatus includes a multiply unit configured to perform multiplications of operands having a particular width. In this embodiment, the apparatus also includes multiple storage elements configured to store operands for the multiply unit. In this embodiment, each of the storage elements is configured to provide a portion of a stored operand that is less than an entirety of the stored operand in response to a control signal from the apparatus. In one embodiment, the apparatus is configured to perform a multiplication of given first and second operands having a width greater than the particular width by performing a sequence of multiply operations using the multiply unit, using portions of the stored operands and without using a carry flag between any of the sequence of multiply operations.

Abstract translation: 公开了关于在没有进位标志的情况下执行扩展乘法的技术。 在一个实施例中，一种装置包括被配置为执行具有特定宽度的操作数的乘法的乘法单元。 在该实施例中，该装置还包括被配置为存储乘法单元的操作数的多个存储元件。 在该实施例中，每个存储元件被配置为响应于来自该设备的控制信号而提供小于存储的操作数的整体的存储操作数的一部分。 在一个实施例中，该装置被配置为通过使用存储的操作数的部分并且不使用进位标志来执行使用乘法单元的乘法运算序列来执行具有大于特定宽度的宽度的给定第一和第二操作数的乘法 在任何一个乘法运算序列之间。