公开(公告)号：US09582276B2

公开(公告)日：2017-02-28

申请号：US13629471

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Gerard R. Williams, III

IPC: G06F9/38 ,  G06F9/52 ,  G06F9/30

CPC classification number: G06F9/30087 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/522

Abstract: Methods and processors for enforcing an order of memory access requests in the presence of barriers in an out-of-order processor pipeline. A speculative color is assigned to instruction operations in the front-end of the processor pipeline, while the instruction operations are still in order. The instruction operations are placed in any of multiple reservation stations and then issued out-of-order from the reservation stations. When a barrier is encountered in the front-end, the speculative color is changed, and instruction operations are assigned the new speculative color. A core interface unit maintains an architectural color, and the architectural color is changed when a barrier retires. The core interface unit stalls instruction operations with a speculative color that does match the architectural color.

Abstract translation: 在无序处理器管道中存在障碍的情况下执行存储器访问请求的顺序的方法和处理器。 在处理器管道的前端分配指令颜色，而指令操作仍然有序。 指令操作被放置在多个保留站中的任一个中，然后从保留站发出无序。 当在前端遇到屏障时，推测颜色发生变化，指令操作会被分配新的投机颜色。 核心接口单元维护建筑颜色，并且在屏障退出时改变架构颜色。 核心接口单元使用与建筑颜色匹配的推测颜色停止指令操作。

公开(公告)号：US20150309792A1

公开(公告)日：2015-10-29

申请号：US14264789

申请日：2014-04-29

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Pradeep Kanapathipillai ,  Sandeep Gupta

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3861

Abstract: Systems, methods, and apparatuses for reducing the load to load/store address latency in an out-of-order processor. When a producer load is detected in the processor pipeline, the processor predicts whether the producer load is going to hit in the store queue. If the producer load is predicted not to hit in the store queue, then a dependent load or store can be issued early. The result data of the producer load is then bypassed forward from the data cache directly to the address generation unit. This result data is then used to generate an address for the dependent load or store, reducing the latency of the dependent load or store by one clock cycle.

Abstract translation: 用于减少在乱序处理器中加载/存储地址延迟的负载的系统，方法和装置。 当在处理器流水线中检测到生产者负载时，处理器预测生产者负载是否要在存储队列中命中。 如果生产者负载被预测不会在商店队列中击中，则可以提前发出依赖负载或商店。 然后，生成器负载的结果数据从数据高速缓存直接旁路到地址生成单元。 然后，该结果数据用于生成相关负载或存储的地址，从而将依赖负载或存储的延迟减少一个时钟周期。

公开(公告)号：US20150026413A1

公开(公告)日：2015-01-22

申请号：US13942780

申请日：2013-07-16

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Gerard R. Williams, III ,  Hari S. Kannan ,  Pavlos Konas

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026 ,  Y02D10/13

Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetcher in which patterns may include wild cards for some cache blocks. The wild card may match any access for the corresponding cache block (e.g. no access, demand access, prefetch, successful prefetch, etc.). Furthermore, patterns with irregular strides and/or irregular access patterns may be included in the matching patterns and may be detected for prefetch generation. In an embodiment, the AMPM prefetcher may implement a chained access map for large streaming prefetches. If a stream is detected, the AMPM prefetcher may allocate a pair of map entries for the stream and may reuse the pair for subsequent access map regions within the stream. In some embodiments, a quality factor may be associated with each access map and may control the rate of prefetch generation.

Abstract translation: 在一个实施例中，处理器可以实现基于访问映射模式匹配（AMPM）的预取器，其中模式可以包括一些高速缓存块的通配符。 通配符可以匹配对应的高速缓存块的任何访问（例如，无访问，请求访问，预取，成功预取等）。 此外，具有不规则步幅和/或不规则访问模式的模式可以被包括在匹配模式中，并且可以被检测用于预取生成。 在一个实施例中，AMPM预取器可以实现用于大型流预取的链接访问映射。 如果检测到流，则AMPM预取器可以为流分配一对映射条目，并且可以将该对重新使用在该流内的后续访问映射区域。 在一些实施例中，质量因子可以与每个访问映射关联，并且可以控制预取生成的速率。

公开(公告)号：US20140089589A1

公开(公告)日：2014-03-27

申请号：US13629471

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Stephan G. Meier ,  Gerard R. Williams, III

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30087 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/522

Abstract: Methods and processors for enforcing an order of memory access requests in the presence of barriers in an out-of-order processor pipeline. A speculative color is assigned to instruction operations in the front-end of the processor pipeline, while the instruction operations are still in order. The instruction operations are placed in any of multiple reservation stations and then issued out-of-order from the reservation stations. When a barrier is encountered in the front-end, the speculative color is changed, and instruction operations are assigned the new speculative color. A core interface unit maintains an architectural color, and the architectural color is changed when a barrier retires. The core interface unit stalls instruction operations with a speculative color that does match the architectural color.

Abstract translation: 在无序处理器管道中存在障碍的情况下执行存储器访问请求的顺序的方法和处理器。 在处理器管道的前端分配指令颜色，而指令操作仍然有序。 指令操作被放置在多个保留站中的任一个中，然后从保留站发出无序。 当在前端遇到屏障时，推测颜色发生变化，指令操作会被分配新的投机颜色。 核心接口单元维护建筑颜色，并且在屏障退出时改变架构颜色。 核心接口单元使用与建筑颜色匹配的推测颜色停止指令操作。