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    Security techniques based on memory timing characteristics
    3.
    发明授权
    Security techniques based on memory timing characteristics 有权

    公开(公告)号：US10776521B2

    公开(公告)日：2020-09-15

    申请号：US15679031

    申请日：2017-08-16

    Applicant: Apple Inc.

    Inventor： Jeremie S. Kim ,  Minesh H. Patel ,  Stephan G. Meier ,  Tyler J. Huberty ,  Onur Mutlu

    IPC: G06F21/71 ,  H04L9/32 ,  G06F21/44 ,  G06F21/73 ,  G06F21/72 ,  H04L29/06

    Abstract: Techniques are disclosed for obtaining data using memory timing characteristics. In some embodiments, a physical unclonable function is used to obtain the data. In various embodiments, a computer system programs a timing parameter of a memory accessible by the computer system to a value that is outside of a specified operable range for the timing parameter. In various embodiments, the computer system performs one or more memory operations to a least a portion of the memory and detects a pattern of errors in the portion of the memory. In some embodiments, the computer system generates a response dependent on the pattern of errors. The response may be used to identify the computer system.

    Prefetch throttling in a multi-core system
    4.
    发明授权
    Prefetch throttling in a multi-core system 有权

    公开(公告)号：US09904624B1

    公开(公告)日：2018-02-27

    申请号：US15093173

    申请日：2016-04-07

    Applicant: Apple Inc.

    Inventor： Tyler J. Huberty ,  Stephan G. Meier ,  Khubaib Khubaib

    IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0811

    CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0875 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/602

    Abstract: In an embodiment, a system may include multiple processors and a cache coupled to the processors. Each processor includes a data cache and a prefetch circuit that may be configured to generate prefetch requests. Each processor may also generate memory operations responsive to cache misses in the data cache. Each processor may transmit the prefetch requests and memory operations to the cache. The cache may queue the memory operations and prefetch requests, and may be configured to detect, on a per-processor basis, occupancy in the queue of memory requests and low confidence prefetch requests from the processor. The cache may determine if the per-processor occupancies exceed one or more thresholds, and may generate a throttle control to the processors responsive to the occupancies. In an embodiment, the cache may generate the throttle control responsive to a history of the last N samples of the occupancies.

    Secondary Prefetch Circuit that Reports Coverage to a Primary Prefetch Circuit to Limit Prefetching by Primary Prefetch Circuit
    5.
    发明申请
    Secondary Prefetch Circuit that Reports Coverage to a Primary Prefetch Circuit to Limit Prefetching by Primary Prefetch Circuit 有权

    公开(公告)号：US20210303471A1

    公开(公告)日：2021-09-30

    申请号：US16832893

    申请日：2020-03-27

    Applicant: Apple Inc.

    Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Nikhil Gupta

    IPC: G06F12/0862

    Abstract: In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch data into a data cache. A primary prefetch circuit may be configured to generate first prefetch requests in response to a demand access, and may be configured to invoke a second prefetch circuit in response to the demand access. The second prefetch circuit may implement a different prefetch mechanism than the first prefetch circuit. If the second prefetch circuit reaches a threshold confidence level in prefetching for the demand access, the second prefetch circuit may communicate an indication to the primary prefetch circuit. The primary prefetch circuit may reduce a number of prefetch requests generated for the demand access responsive to the communication from the second prefetch circuit.

    Prefetch circuit for a processor with pointer optimization
    6.
    发明授权
    Prefetch circuit for a processor with pointer optimization 有权

    公开(公告)号：US10402334B1

    公开(公告)日：2019-09-03

    申请号：US15948072

    申请日：2018-04-09

    Applicant: Apple Inc.

    Inventor： Stephan G. Meier ,  Mridul Agarwal

    IPC: G06F12/00 ,  G06F12/0862 ,  G06F9/30

    Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit with features designed to improve prefetching accuracy and/or reduce power consumption. In an embodiment, the prefetch circuit may be configured to detect that pointer reads are occurring (e.g. “pointer chasing.”) The prefetch circuit may be configured to increase the frequency at which prefetch requests are generated for an access map in which pointer read activity is detected, compared to the frequency at which the prefetch requests would be generated in the pointer read activity is not generated. In an embodiment, the prefetch circuit may also detect access maps that are store-only, and may reduce the frequency of prefetches for store only access maps as compared to the frequency of load-only or load/store maps.

    Unified prefetch circuit for multi-level caches
    7.
    发明授权
    Unified prefetch circuit for multi-level caches 有权

    公开(公告)号：US10180905B1

    公开(公告)日：2019-01-15

    申请号：US15093213

    申请日：2016-04-07

    Applicant: Apple Inc.

    Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Gerard R. Williams, III ,  Pradeep Kanapathipillai

    IPC: G06F12/00 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/0811

    Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit for a multi-level cache system. The access patterns that are matched to the access maps may include prefetches for different cache levels. Centralizing the generation of prefetches into one prefetch circuit may provide better observability and controllability of prefetching at various levels of the cache hierarchy, in an embodiment. Prefetches at different levels may be controlled individually based on the accuracy of those prefetches, in an embodiment. Additionally, in an embodiment, access patterns that are longer that a given threshold may have the granularity of the prefetches change so that more data is prefetched and the prefetches occur farther in advance, in some embodiments.

    SECURITY TECHNIQUES BASED ON MEMORY TIMING CHARACTERISTICS
    8.
    发明申请
    SECURITY TECHNIQUES BASED ON MEMORY TIMING CHARACTERISTICS 审中-公开

    公开(公告)号：US20180307862A1

    公开(公告)日：2018-10-25

    申请号：US15679031

    申请日：2017-08-16

    Applicant: Apple Inc.

    Inventor： Jeremie S. Kim ,  Minesh H. Patel ,  Stephan G. Meier ,  Tyler J. Huberty ,  Onur Mutlu

    IPC: G06F21/71 ,  H04L9/32 ,  G06F21/44

    Abstract: Techniques are disclosed for obtaining data using memory timing characteristics. In some embodiments, a physical unclonable function is used to obtain the data. In various embodiments, a computer system programs a timing parameter of a memory accessible by the computer system to a value that is outside of a specified operable range for the timing parameter. In various embodiments, the computer system performs one or more memory operations to a least a portion of the memory and detects a pattern of errors in the portion of the memory. In some embodiments, the computer system generates a response dependent on the pattern of errors. The response may be used to identify the computer system.

    Pointer chasing prediction
    9.
    发明授权
    Pointer chasing prediction 有权
    指针追逐预测

    公开(公告)号：US09116817B2

    公开(公告)日：2015-08-25

    申请号：US13890716

    申请日：2013-05-09

    Applicant: Apple Inc.

    Inventor： Stephan G. Meier

    IPC: G06F9/38 ,  G06F12/08 ,  G06F9/00

    CPC classification number: G06F12/0862 ,  G06F9/00 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F12/0875

    Abstract: A system and method for efficient scheduling of dependent load instructions. A processor includes both an execution core and a scheduler that issues instructions to the execution core. The execution core includes a load-store unit (LSU). The scheduler determines a first condition is satisfied, wherein the first condition comprises result data for a first load instruction is predicted eligible for LSU-internal forwarding. The scheduler determines a second condition is satisfied, wherein the second condition comprises a second load instruction younger in program order than the first load instruction is dependent on the first load instruction. In response to each of the first condition and the second condition being satisfied, the scheduler can issue the second load instruction earlier than it otherwise would. The LSU internally forwards the received result data from the first load instruction to address generation logic for the second load instruction.

    Abstract translation: 一种用于有效调度依赖负载指令的系统和方法。 处理器包括执行核心和向执行核心发出指令的调度器。 执行核心包括一个加载存储单元（LSU）。 调度器确定满足第一条件，其中第一条件包括用于第一加载指令的结果数据被预测为符合LSU内部转发的条件。 调度器确定满足第二条件，其中第二条件包括程序次序中的第二加载指令比第一加载指令取决于第一加载指令。 响应于满足第一条件和第二条件中的每一个，调度器可以比否则发出第二加载指令。 LSU将接收到的结果数据从第一加载指令内部转发到第二加载指令的地址生成逻辑。

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