公开(公告)号：US12052033B2

公开(公告)日：2024-07-30

申请号：US17863425

申请日：2022-07-13

Applicant: Apple Inc.

Inventor： Roy Roth ,  Yonathan Tate

IPC: H03M13/11 ,  H03M13/29 ,  H03M13/43

CPC classification number: H03M13/1131 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1108 ,  H03M13/2948 ,  H03M13/43

Abstract: A decoder includes circuitry and multiple Variable-Node Circuits (VNCs). The VNCs individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables. The circuitry is configured to receive a code word including variables having m-bit values that was encoded using the ECC, to further receive reliability levels assigned respectively to the variables, to decode the code word by applying to the code word a sequence of iterations, including deciding in a given iteration whether a given VNC is to be processed or skipped in that iteration, depending on the reliability levels assigned to the variables of the given VNC, and, when the given VNC is selected for processing, to make a decision whether or not to update one or more of the variables of the given VNC, and to apply the decision by the given VNC.

公开(公告)号：US20240006014A1

公开(公告)日：2024-01-04

申请号：US17852647

申请日：2022-06-29

Applicant: Apple Inc.

Inventor： Nir Tishbi ,  Roy Roth ,  Yonathan Tate

IPC: G11C29/50 ,  G11C7/10

CPC classification number: G11C29/50004 ,  G11C7/1069 ,  G11C2029/5004

Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.

公开(公告)号：US10389388B2

公开(公告)日：2019-08-20

申请号：US15856107

申请日：2017-12-28

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Tomer Ish-Shalom

IPC: H03M13/37 ,  H03M13/11 ,  H03M13/43 ,  H03M13/39

Abstract: A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.

公开(公告)号：US09853661B2

公开(公告)日：2017-12-26

申请号：US14961913

申请日：2015-12-08

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Asaf Landau ,  Micha Anholt

IPC: H04L1/00 ,  H03M13/11 ,  G06F11/07

CPC classification number: H03M13/1131 ,  G06F11/0727 ,  G06F11/076 ,  H03M13/1128 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116

Abstract: A decoder includes an interface and circuitry. The interface is configured to receive a code word that was encoded using a Quasi-Cyclic Low Density Parity Check (QC-LDPC) Error Correcting Code (ECC) represented by multiple check equations that are defined over multiple variables. The circuitry is configured to decode the code word by iteratively processing multiple layers that each includes a respective subset of the variables of the code word, and producing per each layer one or more count updates, and to generate a total number of errors corrected over the entire code word by accumulating the count updates.

公开(公告)号：US20170338838A1

公开(公告)日：2017-11-23

申请号：US15156356

申请日：2016-05-17

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Moti Teitel

IPC: H03M13/37 ,  H03M13/11 ,  H03M13/45

CPC classification number: H03M13/116 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1128

Abstract: A decoder includes one or more Variable-Node Processors (VNPs) that hold respective variables, and logic circuitry. The logic circuitry is configured to decode a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations such that each iteration involves processing of at least some of the variables, to hold one or more auxiliary equations derived from the check equations, so that a number of the auxiliary equations is smaller than a number of the check equations, to evaluate the auxiliary equations, during the sequence of iterations, using the variables, and, in response to detecting that the variables satisfy the auxiliary equations, to terminate the sequence of iterations and output the variables as the decoded code word.

公开(公告)号：US09595977B2

公开(公告)日：2017-03-14

申请号：US14499284

申请日：2014-09-29

Applicant: APPLE INC.

Inventor： Asaf Landau ,  Tomer Ish-Shalom ,  Yonathan Tate

IPC: H03M13/11 ,  H03M13/27 ,  H04L1/00 ,  H03M13/00 ,  H03M13/15

CPC classification number: H03M13/116 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/15 ,  H03M13/271 ,  H03M13/616 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0057

Abstract: A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.

Abstract translation: 解码器包括可变节点电路，校验节点电路和消息传递（MP）模块，消息传递（MP）模块包括多个可配置的部分循环移位器，每个移位器仅支持移位值0的全范围内的移位值的部分子集。 。 。 L-1。 可变节点电路和校验节点电路被配置为根据表示相应的准循环（QC） - 低密度奇偶校验（LDPC）纠错码（ECC）的奇偶校验矩阵和彼此之间的交换消息 其包括L乘L子矩阵，并处理所交换的消息以解码使用QC-LDPC ECC编码的给定码字。 MP模块被配置为根据相应的子矩阵来调度互连的可变节点电路和校验节点电路，以通过分配给定的部分循环移位器来周期性地移动L个消息来同时交换L个消息 这取决于相应子矩阵的结构。