Abstract:
A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to read from a group of the memory cells a code word encoded using an Error Correction Code (ECC), by sensing the memory cells using at least first and second read thresholds for producing respective first and second readouts, to calculate, based on at least one of the first and second readouts, (i) a syndrome weight that is indicative of an actual number of errors contained in the code word, and (ii) a mid-zone count of the memory cells for which the first readout differs from the second readout, and, to evaluate a performance measure for the memory cells, based on the calculated syndrome weight and mid-zone count.
Abstract:
A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vector s is produced by multiplying the data vector by a data sub-matrix Hs of the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vector s based on a decomposition of a parity sub-matrix Hp of the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as Hp, C is matrix that is smaller than Hp, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation Hp=A+UCV.
Abstract translation:一种用于数据编码的方法包括:根据由奇偶校验矩阵H定义的代码,将要编码的数据向量接收到码字中。通过将数据矢量乘以数据子矩阵Hs 奇偶校验矩阵H.通过基于使用矩阵A,C,U的矩阵H的奇偶校验子矩阵Hp的分解,向中间向量s应用一系列操作来导出码字的奇偶校验部分, V,其中分解A是具有与Hp相同大小的块三角矩阵,C是小于Hp的矩阵,矩阵U和V是选择为使得A,C,U和V满足的放置矩阵 矩阵方程Hp = A + UCV。
Abstract:
A method includes decoding a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations, such that each iteration involves processing of multiple variable nodes. For one or more selected variable nodes, a count of the check equations that are defined over one or more variables held respectively by the one or more selected variable nodes is evaluated, and, when the count meets a predefined skipping criterion, the one or more selected variable nodes are omitted from a given iteration in the sequence.
Abstract:
A method includes programming a group of analog memory cells by writing respective analog values into the memory cells in the group. After programming the group, the analog values are read from the memory cells in the group using a set of read thresholds so as to produce readout results. Respective optimal positions for the read thresholds in the set are identified based on the readout results. A noise level in the readout results is estimated based on the identified optimal positions of the read thresholds.
Abstract:
A method includes, in an Error Correction Code (ECC) decoder that includes variable nodes and check nodes, receiving in a given variable node Check-to-Variable (C2V) messages from a subset of the check nodes. Magnitudes for respective Variable-to-Check (V2C) messages to be sent to the check nodes in the subset are computed based on the received C2V messages. A single sign is computed, for use in all the V2C messages to be sent from the given variable node to the check nodes in the subset. The V2C messages are sent from the given variable node to the check nodes in the subset, such that each V2C message includes a respective magnitude and the single sign.
Abstract:
A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.
Abstract:
An apparatus for data coding includes an encoder and a decoder. The encoder is configured to receive input data including one or more m-bit data groups that are associated with respective group indices, to generate a code word that includes the input data and an m-bit redundancy that depends on the data groups and on the respective group indices, and to send the code word over a channel. The decoder is connected to the channel and is configured to produce a syndrome that equals zero when the code word is error-free, and when the code word contains a single error caused by the channel, is indicative of an erroneous group in which the single error occurred, and of a location of the single error within the erroneous group, and to recover the input data by correcting the single error at the location in the erroneous group.
Abstract:
A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.
Abstract:
A method for data storage includes reading storage values, which represent stored data, from a group of memory cells using read thresholds, and deriving respective soft reliability metrics for the storage values. The storage values are classified into two or more subgroups based on a predefined classification criterion. Independently within each subgroup, a subgroup-specific distribution of the storage values in the subgroup is estimated, and the soft reliability metrics of the storage values in the subgroup are corrected based on the subgroup-specific distribution. The stored data is decoded using the corrected soft reliability metrics.
Abstract:
A method includes, in a decoder of an Error Correction Code (ECC), maintaining only aggregated information regarding a set of messages, a function of which is to be reported from a first node to a second node of the decoder. The function of the set is determined and reported using the aggregated information. After reporting the function, one of the messages in the set is replaced with a new message. The aggregated information is updated to reflect the set having the new message, and the function of the set having the new message is determined and reported using the updated aggregated information.