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    Cache control in presence of speculative read operations
    21.
    发明授权
    Cache control in presence of speculative read operations 有权

    公开(公告)号：US11263133B2

    公开(公告)日：2022-03-01

    申请号：US16979624

    申请日：2019-03-12

    Applicant: Arm Limited

    Inventor： Andreas Lars Sandberg ,  Stephan Diestelhorst ,  Nikos Nikoleris ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Frederic Claude Marie Piry ,  Albin Pierrick Tonnerre

    IPC: G06F12/0802

    Abstract: Coherency control circuitry (10) supports processing of a safe-speculative-read transaction received from a requesting master device (4). The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache (11) of the requesting master device (4) while prohibiting any change in coherency state associated with the target data in other caches (12) in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry (10) and the second cache (12) is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.

    Address decryption for memory storage
    22.
    发明授权
    Address decryption for memory storage 有权

    公开(公告)号：US11176058B2

    公开(公告)日：2021-11-16

    申请号：US16749006

    申请日：2020-01-22

    Applicant: Arm Limited

    Inventor： Andreas Lars Sandberg ,  Derek Del Miller

    IPC: G06F12/14 ,  H04L9/32 ,  H04L9/08 ,  H04L9/30

    Abstract: An apparatus comprises memory storage circuitry comprising a plurality of memory storage locations to store data; an interface to receive an address from a requester; decryption circuitry to obtain a decrypted address by decrypting, based on a decryption key, an address received from the requester; and access control circuitry to select, based on the decrypted address obtained by the decryption circuitry, a memory storage location of the memory storage circuitry to be accessed.

    Partial-address-translation-invalidation request
    24.
    发明授权
    Partial-address-translation-invalidation request 有权

    公开(公告)号：US11853228B1

    公开(公告)日：2023-12-26

    申请号：US17837108

    申请日：2022-06-10

    Applicant: Arm Limited

    Inventor： Andreas Lars Sandberg

    IPC: G06F12/1045 ,  G06F12/0802

    CPC classification number: G06F12/1045 ,  G06F12/0802 ,  G06F2212/60

    Abstract: Partial-address-translation-invalidation request to cause cache control circuitry to: identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicative of an address of the next level page table specified by a table address of a target page table entry when used as the branch page table entry; and trigger an invalidation of the given cache entry when the given cache entry is identified to be the target cache entry. The given cache entry is permitted to be retained when the given cache entry provides full address translation data indicative of an address of a corresponding region of address space corresponding to an output address specified by the target page table entry when used as the leaf page table entry.

    Parallel page table entry access when performing address translations
    27.
    发明授权
    Parallel page table entry access when performing address translations 有权

    公开(公告)号：US10997083B2

    公开(公告)日：2021-05-04

    申请号：US16120637

    申请日：2018-09-04

    Applicant: Arm Limited

    Inventor： Geoffrey Wyman Blake ,  Prakash S. Ramrakhyani ,  Andreas Lars Sandberg

    IPC: G06F12/00 ,  G06F13/00 ,  G06F12/1009 ,  G06F12/0802

    Abstract: Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry. The translation determination comprises: calculating a higher level pointer to the intermediate level page table entry by applying a first predetermined function to the virtual address, calculating the intermediate level pointer by applying a second predetermined function to the virtual address, and initiating a memory access to retrieve in parallel the intermediate level pointer from the intermediate level page table entry and the translation from the last level page table entry.

    Methods and apparatus of cache access to a data array with locality-dependent latency characteristics
    29.
    发明授权
    Methods and apparatus of cache access to a data array with locality-dependent latency characteristics 有权

    公开(公告)号：US10761988B2

    公开(公告)日：2020-09-01

    申请号：US16142330

    申请日：2018-09-26

    Applicant: Arm Limited

    Inventor： Radhika Sanjeev Jagtap ,  Nikos Nikoleris ,  Andreas Lars Sandberg ,  Stephan Diestelhorst

    IPC: G06F12/0864 ,  G06F12/1045

    Abstract: Aspects of the present disclosure relate to an apparatus comprising a data array having locality-dependent latency characteristics such that an access to an open unit of the data array has a lower latency than an access to a closed unit of the data array. Set associative cache indexing circuitry determines, in response to a request for data associated with a target address, a cache set index. Mapping circuitry identifies, in response to the index, a set of data array locations corresponding to the index, according to a mapping in which a given unit of the data array comprises locations corresponding to a plurality of consecutive indices, and at least two locations of the set of locations corresponding to the same index are in different units of the data array. Cache access circuitry accesses said data from one of the set of data array locations.

    Apparatus and method for transferring data between address ranges in memory
    30.
    发明授权
    Apparatus and method for transferring data between address ranges in memory 有权

    公开(公告)号：US10712965B2

    公开(公告)日：2020-07-14

    申请号：US15806580

    申请日：2017-11-08

    Applicant: ARM LIMITED

    Inventor： Andreas Lars Sandberg ,  Nikos Nikoleris ,  David Hennah Mansell

    IPC: G06F3/06 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/0831

    Abstract: An apparatus and method are provided for transferring data between address ranges in memory. The apparatus comprises a data transfer controller, that is responsive to a data transfer request received by the apparatus from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in the memory. A redirect controller is then arranged, whilst the transfer operation is being performed, to intercept an access request that specifies a target address within a target address range, and to perform a memory redirection operation so as to cause the access request to be processed without awaiting completion of the transfer operation. Via such an approach, the apparatus can effectively hide from the source of the access request the fact that the transfer operation is in progress, and hence the transfer operation can be arranged to occur in the background, and in a manner that is transparent to the software executing on the source that has issued the access request.

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