公开(公告)号：US20180183456A1

公开(公告)日：2018-06-28

申请号：US15849227

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link ,  Jianping Wen

IPC: H03M1/46 ,  H03M1/44

CPC classification number: H03M1/462 ,  H03M1/0626 ,  H03M1/08 ,  H03M1/442 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

公开(公告)号：US20180181157A1

公开(公告)日：2018-06-28

申请号：US15852757

申请日：2017-12-22

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Wai Lee

IPC: G05F3/26

CPC classification number: G05F3/262 ,  G05F1/10 ,  G05F3/02 ,  G05F3/26

Abstract: A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.

公开(公告)号：US08643525B1

公开(公告)日：2014-02-04

申请号：US13733301

申请日：2013-01-03

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Amit Kumar ,  Garry N. Link ,  Wai Laing Lee

IPC: H03M1/66

CPC classification number: H03M1/067 ,  H03M1/74 ,  H03M3/502

Abstract: A system and method dynamically selects digital-to-analog (DAC) circuit elements to provide a True differential-output delta-sigma (ΔΣ) DAC. The sign and magnitude of a received N-bit input code is determined. If the input code comprises a positive value, m+r circuit elements are selected from a plurality of circuit elements by a positive element selector, in which comprises a number of rotational elements, and r circuit elements are selected by a negative element selector. Each selected circuit element comprises a circuit element that was not selected for an immediately preceding received input code and has a corresponding minimum usage count value. If the input digital code comprises a negative value, m+r circuit elements are selected by the negative element selector, and r circuit elements are selected by the positive element selector. The circuit elements are capable of being configured as positive or negative circuit elements.

Abstract translation: 一种系统和方法动态地选择数模（DAC）电路元件，以提供真差分输出Δ-Σ（DeltaSigma）DAC。 确定接收到的N位输入代码的符号和大小。 如果输入代码包括正值，则通过正元件选择器从多个电路元件中选择m + r个电路元件，其中包括多个旋转元件，并且r个电路元件由负元件选择器选择。 每个所选择的电路元件包括未被选择用于紧接在前的接收输入代码并且具有对应的最小使用计数值的电路元件。 如果输入数字代码包含负值，则由负选择器选择m + r个电路元件，并且通过正元件选择器选择r个电路元件。 电路元件能够被配置为正或负电路元件。