公开(公告)号：US12073269B2

公开(公告)日：2024-08-27

申请号：US17160718

申请日：2021-01-28

Applicant: Analog Devices International Unlimited Company

Inventor： Roberto S. Maurino

IPC: G06G7/186 ,  H03H19/00 ,  H03M1/44 ,  H03M3/00

CPC classification number: G06G7/1865 ,  G06G7/186 ,  H03H19/004 ,  H03M1/442 ,  H03M3/34 ,  H03M3/458

Abstract: An example SC integrator can include first and second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. The SC integrator can be configured for adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at one or more cycles of a master clock and can be configured for keeping the time distance/delay between those samples relatively small across a range of master clock frequencies.

公开(公告)号：US11770635B2

公开(公告)日：2023-09-26

申请号：US18102941

申请日：2023-01-30

Applicant: Senseics Corporation

Inventor： Ramy S. Tantawy

IPC: H03M1/44 ,  H03M1/12

CPC classification number: H03M1/442 ,  H03M1/129

Abstract: An integrated circuit (IC) includes an analog to digital converter (ADC) circuit having an ADC input and an ADC output. The ADC circuit is configured to receive an input signal at the ADC input and generate a digital output signal at the ADC output based on the input signal. An ADC circuit path is coupled between the ADC input and the ADC output. The ADC circuit comprises a plurality of capacitors coupled between reference voltage sources and the ADC circuit path. The ADC has a reconfigurable resolution and a reconfigurable sampling rate. The ADC circuit is configured to scale the reference voltage sources and/or the plurality of capacitors based on the reconfigurable resolution.

公开(公告)号：US20230179219A1

公开(公告)日：2023-06-08

申请号：US18102941

申请日：2023-01-30

Applicant: Senseics Corporation

Inventor： Ramy Tantawy

IPC: H03M1/44 ,  H03M1/12

CPC classification number: H03M1/442 ,  H03M1/129

Abstract: An integrated circuit (IC) includes an analog to digital converter (ADC) circuit having an ADC input and an ADC output. The ADC circuit is configured to receive an input signal at the ADC input and generate a digital output signal at the ADC output based on the input signal. An ADC circuit path is coupled between the ADC input and the ADC output. The ADC circuit comprises a plurality of capacitors coupled between reference voltage sources and the ADC circuit path. The ADC has a reconfigurable resolution and a reconfigurable sampling rate. The ADC circuit is configured to scale the reference voltage sources and/or the plurality of capacitors based on the reconfigurable resolution.

公开(公告)号：US20180183457A1

公开(公告)日：2018-06-28

申请号：US15849234

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/44 ,  H03M1/08

CPC classification number: H03M1/462 ,  H03M1/0678 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/442 ,  H03M1/468

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：US20180041221A1

公开(公告)日：2018-02-08

申请号：US15555071

申请日：2015-04-09

Applicant: No. 24 Research Institute of China Electronics Technology Group Corporation

Inventor： Daiguo Xu ,  Shiliu Xu ,  Gangyi Hu ,  Guangbing Chen ,  Lu Liu

IPC: H03M1/44 ,  H03M1/12 ,  H03M1/06

CPC classification number: H03M1/442 ,  H03M1/068 ,  H03M1/069 ,  H03M1/1245 ,  H03M1/468

Abstract: An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.

公开(公告)号：US09503118B2

公开(公告)日：2016-11-22

申请号：US15049752

申请日：2016-02-22

Applicant: Jintao Zhang ,  Zhuo Wang ,  Naveen Verma

Inventor： Jintao Zhang ,  Zhuo Wang ,  Naveen Verma

IPC: H03M1/38 ,  H03M1/44

CPC classification number: H03M1/1245 ,  H03M1/1071 ,  H03M1/442 ,  H03M1/466

Abstract: A multiplying analog to digital converter (ADC) including a successive-approximation-register (SAR) analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.

Abstract translation: 包括具有采样输入和反馈输入的逐次逼近寄存器（SAR）模数转换器（ADC）的乘法模数转换器（ADC）和被配置为将ADC输出耦合到 一个数模转换器。 反馈衰减器设置在反馈路径中，反馈衰减器被配置为衰减耦合到反馈输入的反馈信号，该反馈衰减器被配置为提供在ADC输出处观察到的模拟乘法。 桶形移位器被配置为提供ADC输出的数字乘法。 反馈衰减器可以被配置为分频器网络。 反馈衰减器可以被配置为仅使用无源部件来提供衰减。 反馈衰减器可以被配置为电容分压网络。 反馈衰减器可以被配置为提供范围在1和0.5之间的衰减。

公开(公告)号：US09461664B2

公开(公告)日：2016-10-04

申请号：US14090415

申请日：2013-11-26

Applicant: Semiconductor Components Industries, LLC

Inventor： Parthasarathy Sampath

IPC: H04N5/378 ,  H03M1/44 ,  H03M1/10 ,  H03M1/46 ,  H03M1/80

CPC classification number: H03M1/442 ,  H03M1/1038 ,  H03M1/468 ,  H03M1/804

Abstract: Imagers may include analog-to-digital converter circuitry that produces a digital output code from an analog input voltage. The analog-to-digital converter circuitry may include a series of capacitors including a first set of binary-mapped capacitors. The analog-to-digital converter circuitry may include a second set of one or more capacitors that have capacitances that are less than binary-mapped capacitance values. The digital output code may include bits having respective bit positions within the digital output code. During successive-approximation operations performed by the analog-to-digital converter circuitry, each bit of the digital output code may be produced using a corresponding capacitor. Digital processing circuitry such as an image processor may produce a digital value from the digital output code by multiplying the bits of the digital output code with respective weights determined based on the capacitance of the corresponding capacitors.

Abstract translation: 成像器可以包括从模拟输入电压产生数字输出代码的模拟 - 数字转换器电路。 模数转换器电路可以包括包括第一组二进制映射电容器的一系列电容器。 模数转换器电路可以包括具有小于二进制映射电容值的电容的一个或多个电容器的第二组。 数字输出代码可以包括在数字输出代码内具有相应位位置的位。 在由模数转换器电路执行的逐次逼近操作期间，可以使用对应的电容器来产生数字输出代码的每个位。 诸如图像处理器的数字处理电路可以通过将数字输出代码的位乘以基于相应电容器的电容确定的相应权重从数字输出代码产生数字值。

公开(公告)号：US09294116B2

公开(公告)日：2016-03-22

申请号：US14643528

申请日：2015-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajendrakumar Joish

IPC: H03M1/44 ,  H03M1/14 ,  H03M1/66 ,  H03M1/12

CPC classification number: H03M1/442 ,  H03M1/06 ,  H03M1/12 ,  H03M1/145 ,  H03M1/66

Abstract: A circuit includes an amplifier circuit that receives a residue voltage from an output capacitor connected to an output of a digital to analog converter (DAC). The DAC is employed in a pipeline stage of an analog to digital converter (ADC). The amplifier circuit provides a scaled output voltage based on the residue voltage. A sample circuit samples the scaled output voltage during a first portion of a hold phase of the DAC. A discharge circuit supplies the sampled scaled output voltage to the output of the DAC during a second portion of the hold phase of the DAC to mitigate settling time of the DAC.

Abstract translation: 电路包括放大器电路，其从连接到数模转换器（DAC）的输出的输出电容器接收残留电压。 DAC用于模数转换器（ADC）的流水线级。 放大器电路基于残余电压提供缩放的输出电压。 在DAC的保持阶段的第一部分期间，采样电路对缩放的输出电压进行采样。 在DAC的保持阶段的第二部分期间，放电电路将采样的缩放输出电压提供给DAC的输出，以减轻DAC的稳定时间。

公开(公告)号：US20160065229A1

公开(公告)日：2016-03-03

申请号：US14834871

申请日：2015-08-25

Applicant: International Business Machines Corporation

Inventor： Lukas Kull ,  Thomas H. Toifl

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/44

CPC classification number: H03K5/249 ,  H03M1/002 ,  H03M1/1245 ,  H03M1/44 ,  H03M1/442

Abstract: A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit (30) to inject equal charges into the integration nodes.

Abstract translation: 提供了一种用于模数转换器的比较器。 比较器包括差分放大器单元，其基于采样信号提供的电压接收采样信号并提供输出信号。 差分放大器单元包括输入级，其接收采样信号并且基于采样信号的电位对集成节点上的电流进行积分。 比较器包括与集成节点耦合的读出放大器，其检测电位差并放大电位差以产生输出信号。 该比较器包括一个电荷注入电路（30），用于向集成节点注入相等的电荷。

公开(公告)号：US20150349768A1

公开(公告)日：2015-12-03

申请号：US14493635

申请日：2014-09-23

Applicant: Cypress Semiconductor Corporation

Inventor： Eashwar Thiagarajan ,  Harold Kutz ,  Jaskarn Singh Johal ,  Erhan Hancioglu ,  Hans Klein ,  Bruce Byrkett ,  Mark Hastings ,  Dennis Seguine ,  Kendall Castor-Perry ,  Monte Mar ,  Gajender Rohilla

IPC: H03K17/00

CPC classification number: H03K17/00 ,  H03H19/00 ,  H03M1/007 ,  H03M1/068 ,  H03M1/18 ,  H03M1/442 ,  H03M1/468 ,  H03M1/70

Abstract: A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal

Abstract translation: 第一模拟块包括第一多个开关电容器，第二模拟块包括第二多个开关电容器。 可以基于一个或多个模拟功能来配置与第一多个开关电容器相关联的开关以及与第二多个开关电容器相关联的开关。 当模拟功能与第一单端信号相关联时，第一模拟模块和第二模拟模块的配置可以包括与第一多个开关电容器相关联的开关的配置，以及配置与第一多个开关电容器相关联的开关 的开关电容器和与第二多个开关电容器相关联的开关，当模拟功能与差分信号相关联时