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26 条记录 (耗时 0.043 秒)

    Method for improved lithographic patterning utilizing multiple coherency optimized exposures and high transmission attenuated PSM
    23.
    发明授权
    Method for improved lithographic patterning utilizing multiple coherency optimized exposures and high transmission attenuated PSM 有权
    使用多个相干性优化曝光和高透射衰减PSM改进光刻图案的方法

    公开(公告)号：US06951701B2

    公开(公告)日：2005-10-04

    申请号：US10222972

    申请日：2002-08-19

    申请人： Michael Hsu ,  Stephen Hsu ,  Thomas Laidig ,  Douglas Van Den Broeke ,  Jang Fung Chen

    发明人： Michael Hsu ,  Stephen Hsu ,  Thomas Laidig ,  Douglas Van Den Broeke ,  Jang Fung Chen

    IPC分类号： G03F1/00 ,  G03F7/20 ,  H01L21/027 ,  G03B27/72

    CPC分类号： G03F1/32 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/70283 ,  G03F7/70466 ,  G03F7/70591

    摘要： A method for optically transferring a lithographic pattern corresponding to an integrated circuit utilizing a high transmission attenuated phase-shift mask onto a semiconductor substrate by use of an optical exposure tool. The method comprising the steps of generating a diffraction pattern corresponding to the lithographic pattern, where the diffraction pattern indicates a plurality of spatial frequency components corresponding to the lithographic pattern; determining which of the spatial frequency components need to be captured by a lens in the optical exposure tool in order to accurately reproduce the lithographic pattern; determining a set of illumination conditions required for the optical exposure tool to capture the spatial frequency components necessary for accurately reproducing the lithographic pattern; and illuminating the high transmission attenuated phase-shift mask with this set of illumination conditions.

    摘要翻译： 一种通过使用光学曝光工具将对应于利用高透射衰减相移掩模的集成电路的光刻图案光学转移到半导体衬底上的方法。 该方法包括以下步骤：产生对应于光刻图案的衍射图案，其中衍射图案表示对应于光刻图案的多个空间频率分量; 确定哪个空间频率分量需要被光学曝光工具中的透镜捕获，以便准确地再现光刻图案; 确定所述光学曝光工具所需的一组照明条件以捕获准确地再现所述光刻图案所需的空间频率分量; 并用该组照明条件照亮高透射衰减相移掩模。

    Method and apparatus for decomposing semiconductor device patterns into phase and chrome regions for chromeless phase lithography
    25.
    发明申请
    Method and apparatus for decomposing semiconductor device patterns into phase and chrome regions for chromeless phase lithography 有权
    将半导体器件图案分解为无铬相光刻的相位和铬区域的方法和装置

    公开(公告)号：US20050125765A1

    公开(公告)日：2005-06-09

    申请号：US11035737

    申请日：2005-01-18

    申请人： Doug Broeke ,  Jang Chen ,  Thomas Laidig ,  Kurt Wampler ,  Stephen Hsu

    发明人： Doug Broeke ,  Jang Chen ,  Thomas Laidig ,  Kurt Wampler ,  Stephen Hsu

    IPC分类号： G03F1/00 ,  G03F7/20 ,  H01L21/027 ,  G06F17/50 ,  G03F9/00 ,  G21K5/00

    CPC分类号： G03F1/34 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70466 ,  G03F7/70941

    摘要： A method of generating a mask of use in printing a target pattern on a substrate. The method includes the steps of (a) determining a maximum width of features to be imaged on the substrate utilizing phase-structures formed in the mask; (b) identifying all features contained in the target pattern having a width which is equal to or less than the maximum width; (c) extracting all features having a width which is equal to or less than the maximum width from the target pattern; (d) forming phase-structures in the mask corresponding to all features identified in step (b); and (e) forming opaque structures in the mask for all features remaining in target pattern after performing step (c).

    摘要翻译： 一种生成用于在基板上印刷目标图案的掩模的方法。 该方法包括以下步骤：（a）使用形成在掩模中的相位结构来确定要在基板上成像的特征的最大宽度; （b）识别具有等于或小于最大宽度的宽度的目标图案中包含的所有特征; （c）从目标图案提取具有等于或小于最大宽度的宽度的所有特征; （d）在对应于在步骤（b）中识别的所有特征的掩模中形成相位结构; 和（e）在执行步骤（c）之后，在掩模中形成不透明结构以保持目标图案中的所有特征。

    Method and apparatus for minimizing optical proximity effects
    26.
    发明授权
    Method and apparatus for minimizing optical proximity effects 有权

    公开(公告)号：US06519760B2

    公开(公告)日：2003-02-11

    申请号：US09840305

    申请日：2001-04-24

    申请人： Xuelong Shi ,  Jang Fung Chen ,  Stephen Hsu

    发明人： Xuelong Shi ,  Jang Fung Chen ,  Stephen Hsu

    IPC分类号： G06F1750

    CPC分类号： G03F7/705 ,  G03F7/70125 ,  G03F7/70433 ,  G03F7/70441

    摘要： Optical proximity effects (OPEs) are a well-known phenomenon in photolithography. OPEs result from the structural interaction between the main feature and neighboring features. It has been determined by the present inventors that such structural interactions not only affect the critical dimension of the main feature at the image plane, but also the process latitude of the main feature. Moreover, it has been determined that the variation of the critical dimension as well as the process latitude of the main feature is a direct consequence of light field interference between the main feature and the neighboring features. Depending on the phase of the field produced by the neighboring features, the main feature critical dimension and process latitude can be improved by constructive light field interference, or degraded by destructive light field interference. The phase of the field produced by the neighboring features is dependent on the pitch as well as the illumination angle. For a given illumination, the forbidden pitch region is the location where the field produced by the neighboring features interferes with the field of the main feature destructively. The present invention provides a method for determining and eliminating the forbidden pitch region for any feature size and illumination condition. Moreover, it provides a method for performing illumination design in order to suppress the forbidden pitch phenomena, and for optimal placement of scattering bar assist features.