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公开(公告)号：US20230363241A1
公开(公告)日：2023-11-09
申请号：US17633588
申请日：2021-04-21
Inventor： Tongshang SU , Bin ZHOU , Jun CHENG , Qinghe WANG , Ning LIU , Jun WANG , Dacheng ZHANG , Liangchen YAN
IPC: H10K59/80 , H10K59/121 , H10K59/122 , H10K59/126 , H10K59/131 , H10K59/12
CPC classification number: H10K59/80522 , H10K59/1216 , H10K59/122 , H10K59/126 , H10K59/131 , H10K59/1201
Abstract: The present disclosure provides a display substrate, a manufacturing method thereof and a display device. The present disclosure includes a driving circuit layer disposed on a substrate and a light emitting structure layer disposed at one side of the driving circuit layer away from the substrate, wherein the light emitting structure layer includes an anode, an organic light emitting layer, an organic light emitting block, a cathode and an auxiliary electrode, the organic light emitting layer is connected to the anode and the cathode respectively, the auxiliary electrode includes a bottom surface at one side close to the substrate, a top surface at a side away from the substrate and a side surface arranged between the bottom surface and the top surface.
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公开(公告)号：US20210049969A1
公开(公告)日：2021-02-18
申请号：US16994217
申请日：2020-08-14
Inventor： Jun WANG , Liugang ZHOU , Jingang LIU , Ke DAI , Xiaofeng YIN , Jianwei SUN , Liu HE , Zhenlin QU , Qing LI , Yunyun LIANG , Yulong XIONG , Yu QUAN
Abstract: A display driving method includes: determining, by a timing controller, an actual grayscale value of a sub-pixel image in an X-th row and a Y-th column according to a preset grayscale value of a sub-pixel image in an (X−1)-th row and the Y-th column and a preset grayscale value of the sub-pixel image in the X-th row and the Y-th column of an image frame to be displayed. The image frame to be displayed includes J rows and Q columns of sub-pixel images. X is greater than or equal to 2, and is less than or equal to J. Y is greater than or equal to 1, and is less than or equal to Q, and X, Y, J, and Q are all integers.
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公开(公告)号：US20200312881A1
公开(公告)日：2020-10-01
申请号：US15777118
申请日：2017-09-26
IPC: H01L27/12
Abstract: A manufacturing method of a display substrate, an array substrate and a display device are provided. The method includes forming a first wire, a first insulation layer, a first and second metal layer, and a photoresist layer; forming a photoresist retained pattern above the first wire; forming a second and first metal layer retained pattern under the photoresist retained pattern; forming a second insulation layer with a thickness less than or equal to a sum of thicknesses of the first and second metal layer; the second insulation layer forming a fracture region at a boundary between a part covering the first insulation layer and another part covering the second metal layer retained pattern; removing the first and second metal layer retained patterns by a wet etch process to expose the first insulation layer; and forming a contact hole exposing the first wire.
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24.发明申请公开(公告)号：US20190173028A1
公开(公告)日：2019-06-06
申请号：US15991134
申请日：2018-05-29
Inventor： Jun WANG , Guangyao LI , Dongfang WANG , Jun LIU , Guangcai YUAN , Leilei CHENG
Abstract: The present disclosure relates to a substrate, a method for fabricating the same and an organic light emitting diode display device. The substrate includes a metal foil. A metal material used for the metal foil is capable of being anodized and a plurality of concave light trapping microstructures is formed on a surface of the metal foil.
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公开(公告)号：US20240298403A1
公开(公告)日：2024-09-05
申请号：US18560671
申请日：2021-05-13
Inventor： Yunyun LIANG , Changcheng LIU , Jiantao LIU , Liugang ZHOU , Jianwei SUN , Liu HE , Jun WANG , Qing LI , Yu QUAN , Yanting HUANG , Yunlu CHEN , Zhengru PAN
CPC classification number: H05K1/0269 , H05K1/189 , H05K2201/10128 , H05K2201/10318
Abstract: The present disclosure provides a circuit board, a chip on film, a display apparatus and a bonding method. The circuit board has a plurality of bonding regions for bonding with a chip on film, each bonding region includes: a plurality of first pins extending along a first direction and sequentially arranged along a second direction; and at least one first alignment mark group on an arrangement path along which the plurality of first pins are arranged and configured to be aligned with a second alignment mark group of the chip on film in a buckled way, so that the plurality of first pins are bonded and attached to second pins of the chip on film in one-to-one correspondence.
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Patent Agency Ranking
26.发明公开公开(公告)号：US20240233663A9
公开(公告)日：2024-07-11
申请号：US17769632
申请日：2021-03-03
Inventor： Yunlu CHEN , Changcheng LIU , Liugang ZHOU , Liu HE , Kun YANG , Jianwei SUN , Jun WANG , Yunyun LIANG , Qing LI , Yu QUAN , Yanting HUANG , Zhengru PAN , Bingbing YAN , Jiantao LIU
CPC classification number: G09G3/36 , G09G3/2096 , G09G2320/02 , G09G2320/041 , G09G2370/00
Abstract: Disclosed are a method for adjusting a signal of a display panel, a time controller integrated circuit, a display panel, and a storage medium. The method includes: converting first data into a first data voltage signal using a first data voltage, in response to a set condition being reached, sending the first data voltage signal to a chip on film integrated circuit, the chip on film integrated circuit identifies the first data voltage signal to obtain a second data; acquiring the second data from the chip on film integrated circuit, determining that the chip on film integrated circuit fails to identify the first data in response to the second data being different from the first data; and adjusting the first data voltage until a second data voltage signal converted from the first data using a second data voltage after adjustment being successfully identified by the chip on film integrated circuit.
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公开(公告)号：US20240099057A1
公开(公告)日：2024-03-21
申请号：US18275811
申请日：2021-11-18
Inventor： Jun LIU , Jun WANG , Ning LIU , Tongshang SU , Haidong WANG , Bin ZHOU , Xuehai GUI , Rong LIU
IPC: H10K59/12 , H10K59/122 , H10K59/124
CPC classification number: H10K59/1201 , H10K59/122 , H10K59/124
Abstract: A light-emitting panel has a light-emitting area and an isolation area adjacent to the light-emitting area The light-emitting panel comprises a base substrate and a barrier structure, wherein the barrier structure is arranged on one side of the base substrate and located in the isolation area, and comprises a first isolation pattern, a second isolation pattern, a third isolation pattern and a fourth isolation pattern, which are sequentially arranged in a stacked manner, and the first isolation pattern is closer to the base substrate than the fourth isolation pattern; and an orthographic projection of the first isolation pattern on the substrate is located in an orthographic projection of the second isolation pattern on the base substrate, and an orthographic projection of the third isolation pattern on the base substrate is located in an orthographic projection of the fourth isolation pattern on the base substrate.
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公开(公告)号：US20230005430A1
公开(公告)日：2023-01-05
申请号：US17778597
申请日：2021-01-15
Inventor： Guangyao LI , Zheng LIU , Haitao WANG , Jun WANG , Dongfang WANG
IPC: G09G3/3266 , G09G3/3233 , G09G3/20 , G11C19/28
Abstract: Provided are a display substrate and a detection method therefor, and a display apparatus. Compensation sub-circuits that are in one-to-one correspondence with each stage of a shift register are arranged in a gate driving circuit, and a first capacitor in each compensation sub-circuit is thus charged under the control of a detection input circuit when each stage of the shift register outputs a signal stage by stage; and an output control circuit is used to disconnect the compensation sub-circuit from a pull-up node of the corresponding stage of the shift register. The triggering of each stage of the shift register is stopped after each stage of the shift register (CR(n)) completes outputting, and the output control circuit provides a signal of a first power voltage end to the pull-up node of the corresponding stage of the shift register under the control of a second control end and the first capacitor.
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29.发明申请公开(公告)号：US20220415280A1
公开(公告)日：2022-12-29
申请号：US17778125
申请日：2021-05-11
Inventor： Yunyun LIANG , Liugang ZHOU , Ke DAI , Liu HE , Jianwei SUN , Jun WANG , Qing LI , Yu QUAN
IPC: G09G3/36
Abstract: There is provided a voltage supply circuit, in which a signal output end of a power management integrated circuit, a signal input end of a transmission branch, and a signal input end of a voltage reduction branch are coupled to a first node; a signal output end of transmission branch and a signal output end of the voltage reduction branch are coupled to a second node; the power management integrated circuit supplies an initial voltage to the first node; the transmission branch is coupled to a control signal terminal, and switch between a conducting state and a cutoff state in response to control of a control signal, and write the initial voltage into the second node in the conducting state; and the voltage reduction branch performs voltage reduction on the initial voltage at the first node to obtain a reduced voltage to be written into the second node.
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公开(公告)号：US20210359071A1
公开(公告)日：2021-11-18
申请号：US16617962
申请日：2019-03-18
Inventor： Jun WANG , Zhantao WANG , Runmin TANG , Qiancheng ZHAO , Xing REN
Abstract: A display panel, methods for manufacturing and detecting the display panel and a display device are provided. The display panel includes: a substrate, including a display region and a circuit region; multiple signal line terminals in the circuit region, coupled with signal lines respectively; multiple switch elements in the circuit region, first terminals of the switch elements are coupled with the signal line terminals respectively; multiple leads located in the circuit region and on a side of the signal line terminals distal to the display region, spaced apart from each other along a first direction, extending along a second direction, first ends of the leads are coupled with the second terminals of the switch elements respectively, second ends of the leads in the second direction extend to an edge of the substrate, each switch element is configured to connect or disconnect the first terminal and the second terminal thereof.
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