公开(公告)号：US6017795A

公开(公告)日：2000-01-25

申请号：US72996

申请日：1998-05-06

申请人： Chia-Ta Hsieh ,  Jenn Tsao ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

发明人： Chia-Ta Hsieh ,  Jenn Tsao ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.

摘要翻译： 提供了一种用于形成具有减小的尺寸，部分埋入的源极线，增加的源耦合比，改进的可编程性和整体增强性能的分裂栅极快闪存储器单元的方法。 分裂门电池还具有减小的尺寸和改进的性能。 源极线形成在源极区域上的衬底中的沟槽中。 沟槽壁提供增加的源耦合，并且没有门鸟的喙与沟槽一起收缩细胞尺寸。 通过浮动栅极和控制栅极之间的隔间氧化物，通过更有利的热电子注入也可以提高可编程性。

公开(公告)号：US06355527B1

公开(公告)日：2002-03-12

申请号：US09314588

申请日：1999-05-19

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的耦合比和改进的程序速度的分离栅极闪存单元的方法。 还提供了分离栅极单元，其中第一多晶硅层形成布置在形成在形成控制栅极的第二多晶硅层上的中间栅极氧化物上的浮置栅极。 然而，第二多晶硅层也形成在源极区上方并且覆盖浮置栅极的另一个另外暴露的部分，使得该附加多线现在共享源极和浮置栅极之间的电压，从而减少穿通和结击穿 电压。 此外，沿浮置栅极的另一个多壁的存在增加了源极和浮置栅极之间的耦合比，这进而提高了分离栅极闪存单元的编程速度。

公开(公告)号：US06249454B1

公开(公告)日：2001-06-19

申请号：US09396519

申请日：1999-09-15

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.

公开(公告)号：US06207503B1

公开(公告)日：2001-03-27

申请号：US09133970

申请日：1998-08-14

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 以掩模盖的图案形成由隧道氧化物层和浮栅电极层形成的栅电极堆叠。 在覆盖堆叠和源极区域和漏极区域的衬底上方形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 将栅极电极堆叠的中心的源极线槽图案化为衬底。 通过源线槽形成源区。 形成漏极区域与分离栅电极和栅极电极堆叠自对准。

公开(公告)号：US06174772B1

公开(公告)日：2001-01-16

申请号：US09347548

申请日：1999-07-06

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

摘要翻译： 公开了一种形成具有形成在衬垫氧化物上的氮化物间隔物并且之前形成多晶氧化物层的分裂栅极快闪存储器单元的方法。 以这种方式，避免了在形成多晶硅氧化物之前在氮化物间隔物的蚀刻期间多晶氧化物通常会发生的任何损伤。 因此，通过反转形成间隔物和多晶氧化物的顺序，包括首先形成衬垫氧化物，也可以避免由于对下面的间隔物的不可预测的损伤而导致的多晶氧化物厚度的变化 。 结果，对于在同一晶片上以及相同或不同生产线上的不同晶片上制造的单元，都能够防止栅极间闪存单元的擦除速度的变化。

公开(公告)号：US6165845A

公开(公告)日：2000-12-26

申请号：US298931

申请日：1999-04-26

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种形成尖锐的多晶硅尖端以提高分流栅闪存的速度的方法。 提供尖锐的多头尖端来代替常规的门鸟嘴（GBB），因为后者需要形成在超级集成技术的小型化电路中越来越困难的厚的多晶氧化物。 此外，众所周知，GBB在分割门闪存中的栅极边缘下侵入并降低亚微米存储器单元的可编程性。 通过高压蚀刻形成锥形浮栅，使得多晶氧化物下方的浮栅的上边缘的尖端更清晰，更坚固，因此不易受损害，从而提供本发明的尖锐的多尖端 在电池的制造期间。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US6093608A

公开(公告)日：2000-07-25

申请号：US298142

申请日：1999-04-23

申请人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

发明人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate. The P-channel flash memory cell has a higher impact ionization rage for creating hot electrons so that the distance between the source and drain junctions and the length of the floating gate can be kept small thereby permitting the dimensions of the flash memory cell to be shrunk.

公开(公告)号：US07001809B2

公开(公告)日：2006-02-21

申请号：US10119327

申请日：2002-04-09

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

公开(公告)号：US6130132A

公开(公告)日：2000-10-10

申请号：US55439

申请日：1998-04-06

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： The following steps are used to form a split gate electrode MOS FET device. Form a tunnel oxide layer over a semiconductor substrate. Over the tunnel oxide layer, form a doped first polysilicon layer with a top surface upon which a native oxide forms. Then as an option, remove the native oxide layer. On the top surface of the first polysilicon layer, form a silicon nitride layer and etch the silicon nitride layer to form it into a cell-defining layer. Form a polysilicon oxide dielectric cap over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, etch the first polysilicon layer and the tunnel oxide layer to form a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Form spacers on the sidewalls of the gate electrode stack. Then form blanket inter-polysilicon dielectric and blanket control gate layers covering exposed portions of the substrate and covering the stack. Pattern the inter-polysilicon dielectric and control gate layers into a split gate electrode pair. Form a source region self-aligned with the floating gate electrode stack; perform a tungsten silicide anneal; and form a drain region self-aligned with the control gate electrodes.

摘要翻译： 以下步骤用于形成分离栅电极MOS FET器件。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成掺杂的第一多晶硅层，其上形成有天然氧化物的顶表面。 然后作为选项，删除自然氧化物层。 在第一多晶硅层的顶表面上，形成氮化硅层并蚀刻氮化硅层以形成单元限定层。 在第一多晶硅层的顶表面上形成多晶硅氧化物电介质盖。 除了多晶硅氧化物盖之外，蚀刻第一多晶硅层和隧道氧化物层以形成掩模帽图案中的浮栅电极堆叠，在浮栅电极的外围形成尖锐的峰。 在栅极电极堆叠的侧壁上形成间隔物。 然后形成覆盖基板的暴露部分并覆盖堆叠的覆盖层间多晶硅电介质和覆盖层控制栅极层。 将多晶硅间介质和控制栅极层图案化成分离栅电极对。 形成与浮栅电极堆叠自对准的源区; 进行硅化钨退火; 并形成与控制栅电极自对准的漏区。

公开(公告)号：US6117733A

公开(公告)日：2000-09-12

申请号：US193670

申请日：1998-11-17

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L21/336 ,  H01L29/72 ,  H01L31/00

CPC分类号： H01L29/42324 ,  H01L27/11519 ,  H01L27/11521

摘要： A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch is formed after wet oxidizing the sidewalls of the underlying first polysilicon layer, thus at the same time forming a poly tip which is exposed upwardly but covered by polyoxide on the side. In another embodiment, the notch is formed prior to the oxidation of the exposed regions of the first polysilicon layer, such as the sidewalls, so that during the subsequent oxidation, not only the sidewalls but also the exposed portions of the polysilicon in the notch region are also oxidized. Because the oxidation of the polysilicon advances in a non-uniform manner with very little at the polysilicon/nitride interface and to a larger rate elsewhere, a thin and robust polysilicon tip is formed which is at the same time covered by oval-shaped poly-oxide on all sides. A method of forming a self-aligned source (SAS) line is also disclosed in conjunction with the forming of the polytip. Hence the combination of an enhanced poly tip with a self-aligned source provides a faster split-gate flash memory device.

摘要翻译： 公开了一种用于形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多头）的新方法。 通过在覆盖第一多晶硅层的氮化物层中以两种不同的方式形成凹口来进一步增强多晶硅尖端。 在一个实施例中，凹陷是在湿氧化下面的第一多晶硅层的侧壁之后形成的，因此同时形成向上暴露但被侧面被多氧化物覆盖的多边尖端。 在另一个实施例中，在第一多晶硅层（例如侧壁）的暴露区域的氧化之前形成凹口，使得在随后的氧化期间，不仅侧壁而且在凹口区域中的多晶硅的暴露部分 也被氧化。 由于多晶硅的氧化以非均匀的方式在多晶硅/氮化物界面处以非常小的速度前进，并且在其它地方以更大的速率前进，形成了薄而坚固的多晶硅尖端，同时被椭圆形多晶硅/ 氧化物在所有方面。 结合形成聚丝片也公开了形成自对准源（SAS）线的方法。 因此，增强型多头尖端与自对准源的组合提供了更快的分离栅极闪存器件。