公开(公告)号：US07966474B2

公开(公告)日：2011-06-21

申请号：US12036520

申请日：2008-02-25

申请人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

发明人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

IPC分类号： G06F9/26

CPC分类号： G06F9/3017 ,  G06F9/30018 ,  G06F9/30101 ,  G06F9/355

摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

摘要翻译： 一种用于计算机系统中的翻译的系统，方法和计算机程序产品。 该系统包括包含地址转换表的基地址的通用寄存器。 该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。 该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。 该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

公开(公告)号：US07412476B2

公开(公告)日：2008-08-12

申请号：US11460296

申请日：2006-07-27

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr.

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr.

IPC分类号： G06F7/523

CPC分类号： G06F9/3001 ,  G06F7/496

摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.

摘要翻译： 一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。 部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍 乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

公开(公告)号：US07490121B2

公开(公告)日：2009-02-10

申请号：US11749239

申请日：2007-05-16

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

IPC分类号： G06F7/52

CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.

摘要翻译： 在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

公开(公告)号：US07200742B2

公开(公告)日：2007-04-03

申请号：US11055193

申请日：2005-02-10

申请人： Fadi Y. Busaba ,  Michael J. Mack ,  John G. Rell, Jr. ,  Eric M. Schwarz ,  Chung-Lung K. Shum ,  Timothy J. Slegel ,  Scott B. Swaney ,  Sheryll H. Veneracion

发明人： Fadi Y. Busaba ,  Michael J. Mack ,  John G. Rell, Jr. ,  Eric M. Schwarz ,  Chung-Lung K. Shum ,  Timothy J. Slegel ,  Scott B. Swaney ,  Sheryll H. Veneracion

IPC分类号： G06F9/38

CPC分类号： G06F9/4812 ,  G06F9/30101 ,  G06F9/3863 ,  G06F2209/481

摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.

摘要翻译： 一种用于创建精确异常的方法，包括检查指向引起异常的指令。 检查点导致当前检查点状态。 当前检查点状态被锁定。 确定多个寄存器中的任一个是否需要恢复到当前检查点状态。 响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。 执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。

公开(公告)号：US07167968B2

公开(公告)日：2007-01-23

申请号：US10834637

申请日：2004-04-29

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Mark A. Check ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Frank Tanzi

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Mark A. Check ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Frank Tanzi

IPC分类号： G06F12/06

CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3824 ,  G06F12/0886

摘要： A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.

摘要翻译： 在指令执行期间预先对准用于存储的数据的方法通过消除数据对准所需的周期来提高性能。 该方法可以在ASCII和Packed Decimal格式之间以及Unicode Basic Latin和Packed Decimal格式之间转换数据。 转换为打包十进制硬件需要十进制格式，用于生成十进制结果的微处理器。 从包装十进制转换为ASCII和Unicode基本拉丁文需要以应用程序所需的格式报告十进制算术结果。 为了进一步提高性能，利用固定点单元（FXU）中的所有可用写入端口来减少存储结果所需的周期数。 为了防止数据获取未使用的目标数据缓慢的指令执行，目标位置被测试存储访问异常，但是这些操作数的数据实际上并没有被提取。 从FXU到操作数缓冲区的单个读取请求在单个周期中有效读取整个目标地址（最多8个双字的数据）。

公开(公告)号：US07167889B2

公开(公告)日：2007-01-23

申请号：US10436392

申请日：2003-05-12

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr.

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr.

IPC分类号： G06F7/523

CPC分类号： G06F9/3001 ,  G06F7/496

摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.

摘要翻译： 一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。 部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍 乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

公开(公告)号：US07853635B2

公开(公告)日：2010-12-14

申请号：US11749224

申请日：2007-05-16

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

IPC分类号： G06F7/38 ,  G06F7/52

CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

摘要翻译： 超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

公开(公告)号：US07266580B2

公开(公告)日：2007-09-04

申请号：US10435976

申请日：2003-05-12

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

IPC分类号： G06F7/52

CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

摘要： A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-full sized multiplier employing Booth or other type of recoding methods upon the multiplier to reduce the number of partial products per scan, and implemented in such a manner so that a multiplication operation with large operands may be broken into subgroups of operations that will fit into this mid-sized multiplier whose results, here called modular products, may be knitted back together to form a correct, final product. The second part of the concept is the supporting hardware used to separate the operands into subgroups and input the data and control signals to the multiplier, and the algorithms and apparatuses used to align and combine the modular products properly to obtain the final product. These algorithms used to obtain a result as specified by the operation may be as varied as the supporting hardware with which the multiplier may be used, making this multiplier a very flexible and powerful design.

摘要翻译： 本文中讨论了用于对具有各种长度的有符号和无符号操作数进行二进制乘法的方法和装置。 这是一个概念，可以分为两部分，第一部分是乘法硬件本身，紧凑型，小于满量程的乘法器，在乘数上使用Booth或其他类型的重新编码方法，以减少每个部分产品的数量 扫描和实现，使得具有大操作数的乘法运算可以被分解成适合于该中型乘法器的操作子组，其结果（这里称为模块化产品）可以针织在一起以形成正确的， 完成品。 该概念的第二部分是用于将操作数分成子组并将数据和控制信号输入到乘法器的支持硬件，以及用于对准和组合模块化产品以获得最终产品的算法和装置。 用于获得由操作指定的结果的这些算法可以与可以使用乘法器的支持硬件一样变化，使得该乘法器是非常灵活和强大的设计。

公开(公告)号：US07149767B2

公开(公告)日：2006-12-12

申请号：US10436322

申请日：2003-05-12

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr.

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr.

IPC分类号： G06F7/535

CPC分类号： G06F7/4917

摘要： A method of decimal division in a superscalar processor comprising: obtaining a first operand and a second operand; establishing a dividend and a divisor from the first operand and the second operand; determining a quotient digit and a resulting partial remainder; based on multiple parallel/simultaneous subtractions of at least one of the divisor and a multiple of the divisor from the dividend, utilizing dataflow elements of multiple execution pipes of the superscalar processor.

摘要翻译： 一种超标量处理器中的十进制除法的方法，包括：获得第一操作数和第二操作数; 从第一操作数和第二操作数建立股息和除数; 确定商数和产生的部分余数; 基于超分量处理器的多个执行管道的数据流元素，基于多个并行/同时减除除数的除数和除数的倍数。

公开(公告)号：US07085917B2

公开(公告)日：2006-08-01

申请号：US10435983

申请日：2003-05-12

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Timothy J. Slegel

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Timothy J. Slegel

IPC分类号： G06F9/30 ,  G06F15/00

CPC分类号： G06F9/325 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3885

摘要： In a computer system, a method and apparatus for dispatching and executing multi-cycle and complex instructions. The method results in maximum performance for such without impacting other areas in the processor such as decode, grouping or dispatch units. This invention allows multi-cycle and complex instructions to be dispatched to one port but executed in multiple execution pipes without cracking the instruction and without limiting it to a single execution pipe. Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). The FXU logic then execute these instructions on the available FXU pipes. This method results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.

摘要翻译： 在计算机系统中，用于调度和执行多周期和复杂指令的方法和装置。 该方法导致最大的性能，而不会影响处理器中的其他区域，如解码，分组或调度单元。 本发明允许将多周期和复杂指令分派到一个端口，但是在多个执行管道中执行，而不会破坏指令，而不限于单个执行管道。 在调度单元中生成一些控制信号，并通过指令发送到定点单元（FXU）。 然后，FXU逻辑在可用的FXU管道上执行这些说明。 这种方法导致最佳性能，很少或没有其他并发症。 所提出的技术使得如何在实际执行的FXU中执行这些指令的灵活性，而不是在指令解码或调度单元中或由编译器破解。