公开(公告)号：US09229722B2

公开(公告)日：2016-01-05

申请号：US13362513

申请日：2012-01-31

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F9/38 ,  G06F9/32 ,  G06F9/52

CPC分类号： G06F9/3804 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/322 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/46 ,  G06F9/466 ,  G06F9/467 ,  G06F9/528

摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

公开(公告)号：US09021493B2

公开(公告)日：2015-04-28

申请号：US13615704

申请日：2012-09-14

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/50

CPC分类号： G06F9/5038 ,  G06F9/38 ,  G06F9/45533 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5077 ,  G06F2009/45591 ,  G06F2209/483 ,  G06F2209/5021 ,  G06F2209/504 ,  G06F2209/507 ,  G06F2209/508 ,  Y02B70/30 ,  Y02D10/22

摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

公开(公告)号：US20140082625A1

公开(公告)日：2014-03-20

申请号：US13615704

申请日：2012-09-14

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F9/50

CPC分类号： G06F9/5038 ,  G06F9/38 ,  G06F9/45533 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5077 ,  G06F2009/45591 ,  G06F2209/483 ,  G06F2209/5021 ,  G06F2209/504 ,  G06F2209/507 ,  G06F2209/508 ,  Y02B70/30 ,  Y02D10/22

摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

摘要翻译： 计算环境中的资源例如通过硬件控制器进行管理，硬件控制器控制从用于执行线程的一个或多个资源池中调度资源。 所述控制包括基于所述池中的资源相对于相关联的资源使用阈值的当前使用情况，将资源从所述池有条件地调度到所述计算环境的一个或多个低优先级线程。 该管理还包括监视从该池到该计算环境的一个或多个高优先级线程的资源调度，并且基于该监视，动态地调整在从池中有条件地分派资源中使用的资源使用阈值 ）到低优先级线程。

公开(公告)号：US20140019803A1

公开(公告)日：2014-01-16

申请号：US13548448

申请日：2012-07-13

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F11/14

CPC分类号： G06F11/1479 ,  G06F11/1438

摘要： A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state.

摘要翻译： 计算机系统包括同时多线程处理器和与处理器可操作地通信的存储器。 处理器被配置为执行包括同时运行多个线程的方法，检测处理电路的一个或多个硬件结构中的硬件错误，以及识别多个线程的一个或多个受害者线程。 所述处理器还被配置为识别与所述一个或多个受害者线程的执行相关联的多个硬件结构，通过所述多个线程阻止对所述多个硬件结构的访问来将所述一个或多个受害者线程与所述多个线程的其余部分隔离 通过重置多个硬件结构的硬件状态来刷新一个或多个受害者线程，并通过将多个硬件结构恢复到已知的安全状态来恢复一个或多个受害者线程。

公开(公告)号：US20130191599A1

公开(公告)日：2013-07-25

申请号：US13354894

申请日：2012-01-20

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F12/12

CPC分类号： G06F12/0875 ,  G06F12/126

摘要： A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.

摘要翻译： 提供了用于高速缓存的高速缓存管理的技术。 处理电路在先前执行请求数据元素存储在高速缓存中的指令期间确定未命中和命中位置字段。 针对与请求存储数据元素的指令相对应的数据元素存储未命中和命中位置字段。 处理电路基于错过次数和/或命中位置字段将数据元素放置成分层次序。 命中位置字段包括与缓存中的数据元素相关的分层位置。

公开(公告)号：US08161091B2

公开(公告)日：2012-04-17

申请号：US12358911

申请日：2009-01-23

申请人： Steven R. Carlough ,  Wen H. Li ,  Eric M. Schwarz

发明人： Steven R. Carlough ,  Wen H. Li ,  Eric M. Schwarz

IPC分类号： G06F7/485

CPC分类号： G06F7/4912 ,  G06F2207/4911

摘要： A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second register. An operation, either addition or subtraction, associated with the first operand and the second operand is received. Three concurrent calculations are performed on the first operand and the second operand. The three concurrent calculations include: applying the operation to the first operand and the second operand based on a first assumption; applying the operation to the first operand and the second operand based on a second assumption; and applying the operation to the first operand and the second operand based on a third assumption. A final result is selected from the first result, the second result and the third result.

摘要翻译： 一种用于执行十进制浮点运算的方法，包括将具有第一系数和第一指数的第一操作数接收到第一寄存器中。 具有第二系数和第二指数的第二操作数被接收到第二寄存器中。 接收与第一操作数和第二操作数相关联的加法或减法操作。 在第一个操作数和第二个操作数上执行三个并发计算。 三个并发计算包括：基于第一假设将操作应用于第一操作数和第二操作数; 基于第二假设将操作应用于第一操作数和第二操作数; 以及基于第三假设将所述操作应用于所述第一操作数和所述第二操作数。 从第一个结果，第二个结果和第三个结果中选择最终结果。

公开(公告)号：US20100306632A1

公开(公告)日：2010-12-02

申请号：US12472519

申请日：2009-05-27

申请人： Steven R. Carlough ,  Mark A. Erle ,  Michael R. Kelly

发明人： Steven R. Carlough ,  Mark A. Erle ,  Michael R. Kelly

IPC分类号： H03M13/11 ,  G06F11/10

CPC分类号： H03M7/12 ,  H03M13/09

摘要： Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits.

摘要翻译： 使用二进制编码十进制（BCD）和密集十进制（DPD）转换中的奇偶校验的误差检测，包括具有由处理电路可读的有形存储介质的计算机程序产品，并且存储由处理电路执行以执行方法的指令。 该方法包括以第一格式接收格式化的十进制数据，格式化的十进制数据由DPD格式数据或BCD格式数据组成。 通过将接收到的数据转换成格式化的十进制数据的第二格式，并且通过确定第二格式的数据的奇偶校验来生成一个或多个第一奇偶校验位。 从接收的数据直接生成一个或多个第二奇偶校验位。 响应于第一奇偶校验位不等于第二奇偶校验位，错误标志被设置为指示第二格式的数据中的错误。

公开(公告)号：US07698352B2

公开(公告)日：2010-04-13

申请号：US11227515

申请日：2005-09-15

申请人： Steven R. Carlough ,  Eric M. Schwarz ,  Sheryll H. Veneracion

发明人： Steven R. Carlough ,  Eric M. Schwarz ,  Sheryll H. Veneracion

IPC分类号： G06F15/00

CPC分类号： H03M7/24 ,  H03M7/04

摘要： A system and method for converting from scaled binary coded decimal (SBCD) into decimal floating point (DFP). The system includes a mechanism for receiving one or more of an exponent part of a SBCD number and a coefficient part of the SBCD number. The system also includes at least one of a mechanism for performing coefficient compression on the coefficient part of the SBCD number to create a coefficient part of a DFP number and a mechanism for performing exponent insertion including inserting the exponent part of the SBCD number into an exponent part of the DFP number.

摘要翻译： 从缩放二进制编码十进制（SBCD）转换为十进制浮点（DFP）的系统和方法。 该系统包括用于接收SBCD号的指数部分和SBCD号的系数部分中的一个或多个的机构。 该系统还包括用于对SBCD号码的系数部分执行系数压缩以创建DFP号码的系数部分的机制和用于执行指数插入的机制中的至少一个，包括将SBCD号码的指数部分插入指数 DFP编号的一部分。

公开(公告)号：US20090210659A1

公开(公告)日：2009-08-20

申请号：US12032105

申请日：2008-02-15

申请人： Steven R. Carlough ,  Adam B. Collura ,  Wen H. Li ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

发明人： Steven R. Carlough ,  Adam B. Collura ,  Wen H. Li ,  Eric M. Schwarz ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/30 ,  G06F9/44

CPC分类号： G06F9/3861 ,  G06F9/3017 ,  G06F9/322 ,  G06F9/328 ,  G06F11/0721 ,  G06F11/0793

摘要： A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw.

摘要翻译： 处理器包括用于处理加工缺陷的微架构，所述微体系结构包括：至少一个检测器，适于检测与所述处理缺陷相关联的预定状态; 以及至少一种修改默认处理器处理行为的机制; 并且在修改处理行为时，可以通过避免处理缺陷来完成涉及处理缺陷的指令的处理。

公开(公告)号：US20090132628A1

公开(公告)日：2009-05-21

申请号：US12358885

申请日：2009-01-23

申请人： Steven R. Carlough ,  Paulomi Kadakia ,  Wen H. Li ,  Eric M. Schwarz

发明人： Steven R. Carlough ,  Paulomi Kadakia ,  Wen H. Li ,  Eric M. Schwarz

IPC分类号： G06F7/52

CPC分类号： G06F7/4917 ,  G06F2207/5352

摘要： A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers.

摘要翻译： 一种用于执行小数除法的方法，包括将输入寄存器中的缩放除数和缩放的除数接收。 缩放除数的倍数的子集存储在多个多个寄存器中。 商数是根据缩放除数和缩放除数计算的。 每个商数由流水线机构在三个时钟周期内计算。 计算包括选择新的商数，并计算新的余数。 计算新余数的输入包括来自一个或多个多个寄存器的数据。