公开(公告)号：US20060270152A1

公开(公告)日：2006-11-30

申请号：US11164804

申请日：2005-12-06

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim

IPC分类号： H01L21/8242

CPC分类号： H01L21/28273 ,  H01L27/11521

摘要： Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly gates, forming a spacer at the side of the poly gate, forming a sacrifice nitride film on the entire surface, and then forming an interlayer insulation film on the entire surface, polishing the sacrifice nitride film formed on the interlayer insulation film and the poly gates so that the nitride film is exposed, removing top portions of the sacrifice nitride film while removing the nitride film, forming an insulation film spacer at the side exposed through removal of the nitride film, and filling a portion from which the sacrifice oxide film is removed with an insulation film, and forming the tungsten gates in portions from which the nitride films are moved.

摘要翻译： 这里公开了半导体器件的制造方法。 该方法包括在半导体衬底上形成栅极氧化膜，多晶硅膜和氮化物膜的步骤，以及对栅极氧化膜，多晶硅膜和氮化物膜进行构图以形成多晶硅栅极，在 在整个表面上形成牺牲氮化物膜，然后在整个表面上形成层间绝缘膜，研磨在层间绝缘膜和多晶硅栅上形成的牺牲氮化物膜，使得氮化物膜露出，去除 牺牲氮化物膜的顶部，同时去除氮化物膜，在通过去除氮化物膜暴露的一侧形成绝缘膜间隔物，并且用绝缘膜填充去除牺牲氧化物膜的部分，并形成钨 栅极在其中移动氮化物膜的部分中。

公开(公告)号：US07977205B2

公开(公告)日：2011-07-12

申请号：US12815317

申请日：2010-06-14

申请人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。 在每个第一沟槽的侧壁上形成防氧化间隔物。 第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。 第二沟槽填充有第二氧化物层。 第一沟槽填充有绝缘层。

公开(公告)号：US07736991B2

公开(公告)日：2010-06-15

申请号：US11617690

申请日：2006-12-28

申请人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 间隔件形成在每个第一沟槽的侧壁上。 第二沟槽形成在对应的第一沟槽下方的隔离区域中。 每个第二沟槽比相应的第一沟槽更窄和更深。 第一氧化物层形成在每个第二沟槽的侧壁和底表面上。 第一沟槽填充有绝缘层。

公开(公告)号：US07897504B2

公开(公告)日：2011-03-01

申请号：US11747444

申请日：2007-05-11

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho ,  Seong Hwan Myung

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho ,  Seong Hwan Myung

IPC分类号： H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/28273

摘要： A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

摘要翻译： 一种制造半导体器件的方法，其中可以防止在具有拉伸应力的蚀刻层上形成非晶碳膜而发生提升现象。 根据本发明，由于可以减小蚀刻层或非晶碳膜上的压缩应力，或者在蚀刻层或非晶碳膜之间形成压缩应力膜，以防止发生升降现象，因此可以是其他图案 形成以制造高度集成的半导体器件。

公开(公告)号：US20080003724A1

公开(公告)日：2008-01-03

申请号：US11647628

申请日：2006-12-29

申请人： Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung ,  Cheol Mo Jeong

发明人： Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung ,  Cheol Mo Jeong

IPC分类号： H01L21/8232

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.

摘要翻译： 一种制造闪速存储器件的方法包括以下步骤：在半导体衬底上形成用于单元的栅极图案和用于选择晶体管的栅极图案，在包含栅极图案的所得表面上形成缓冲绝缘层，形成绝缘层以形成空隙 用于单元的栅极图案之间的间隔，在绝缘层上形成氮化物层，并且通过间隔物蚀刻工艺在用于选择晶体管的每个栅极图案的一侧上形成间隔物。

公开(公告)号：US07629213B2

公开(公告)日：2009-12-08

申请号：US11647628

申请日：2006-12-29

申请人： Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung ,  Cheol Mo Jeong

发明人： Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung ,  Cheol Mo Jeong

IPC分类号： H01L21/8238

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.

摘要翻译： 一种制造闪速存储器件的方法包括以下步骤：在半导体衬底上形成用于单元的栅极图案和用于选择晶体管的栅极图案，在包含栅极图案的所得表面上形成缓冲绝缘层，形成绝缘层以形成空隙 用于单元的栅极图案之间的间隔，在绝缘层上形成氮化物层，并且通过间隔物蚀刻工艺在用于选择晶体管的每个栅极图案的一侧上形成间隔物。

公开(公告)号：US20090283818A1

公开(公告)日：2009-11-19

申请号：US12464947

申请日：2009-05-13

申请人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Gyeong Jang

发明人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Gyeong Jang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, the dielectric layer having a groove for exposing the isolation layer, a trench formed on the isolation layer and exposed through the groove, and a second conductive layer formed over the dielectric layer the trench.

摘要翻译： 闪速存储器件包括形成在半导体衬底的隔离区上的隔离层，形成在半导体衬底的有源区上的隧道绝缘层，形成在隧道绝缘层上的第一导电层，形成在第一 所述绝缘层具有用于暴露所述隔离层的沟槽，形成在所述隔离层上并通过所述沟槽露出的沟槽以及在所述电介质层上形成所述沟槽的第二导电层。

公开(公告)号：US20090098740A1

公开(公告)日：2009-04-16

申请号：US12163328

申请日：2008-06-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76232

摘要： The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 该方法包括提供其中形成有沟槽的半导体衬底; 在沟槽中形成第一绝缘层; 以及在所述第一绝缘层上形成致密的第二绝缘层。 在上述方法中，在隔离层中不会产生空隙，因此可以减少或防止有源区的弯曲现象来改善半导体的电特性。

公开(公告)号：US20080268612A1

公开(公告)日：2008-10-30

申请号：US11962611

申请日：2007-12-21

申请人： Whee Won Cho ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Suk Joong Kim ,  Jong Hye Cho

发明人： Whee Won Cho ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Suk Joong Kim ,  Jong Hye Cho

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer. An O3-TEOS layer on the exposed semiconductor substrate which is a bottom surface of the trench is grown faster than that on a surface of the spacer formed of an oxide layer or a nitride layer to prevent the O3-TEOS layers grown on the side walls from coming into contact with each other, and so it is possible to inhibit a generation of a seam and to enhance a gap-filling characteristic for the trench.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 特别地，本发明的半导体器件中形成隔离层的方法包括以下步骤：提供其上形成有沟槽的半导体衬底; 在沟槽的侧壁上形成间隔物; 形成第一绝缘层以填充所述沟槽的一部分，使得作为所述沟槽的底表面并暴露在所述间隔物之间​​的所述半导体衬底上的沉积速率高于所述空间的表面上的沉积速率; 以及在所述第一绝缘层上形成第二绝缘层以便用所述第二绝缘层填充所述沟槽。 作为沟槽底面的暴露的半导体衬底上的O 3 -TOS层比由氧化物层或氮化物层形成的间隔物的表面上生长得快，以防止O 在侧壁上生长的3层以上的层彼此接触，因此可以抑制接缝的产生并且增强沟槽的间隙填充特性。

公开(公告)号：US20080102622A1

公开(公告)日：2008-05-01

申请号：US11647088

申请日：2006-12-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho ,  Seong Hwan Myung

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho ,  Seong Hwan Myung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A method of forming a metal line in a semiconductor device, including the steps of forming a metal line in a semiconductor device in which dummy patterns are formed on a dummy region by using non-metal material when a metal line is formed through a damascene process to prevent a formation of an oxide layer on an aluminum layer caused by a slurry and cleaning solution used in the chemical mechanical polishing (CMP) process and carry out an uniform polishing process, whereby it is possible to prevent a digging phenomenon on a metal layer from being generated.

摘要翻译： 一种在半导体器件中形成金属线的方法，包括以下步骤：在通过镶嵌工艺形成金属线时，通过使用非金属材料在虚拟区域上形成虚拟图案的半导体器件中形成金属线 以防止由化学机械抛光（CMP）工艺中使用的浆料和清洗液在铝层上形成氧化物层，并进行均匀的抛光工艺，从而可以防止在金属层上的挖掘现象 从被生成。