公开(公告)号：US07977205B2

公开(公告)日：2011-07-12

申请号：US12815317

申请日：2010-06-14

申请人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。 在每个第一沟槽的侧壁上形成防氧化间隔物。 第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。 第二沟槽填充有第二氧化物层。 第一沟槽填充有绝缘层。

公开(公告)号：US07736991B2

公开(公告)日：2010-06-15

申请号：US11617690

申请日：2006-12-28

申请人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 间隔件形成在每个第一沟槽的侧壁上。 第二沟槽形成在对应的第一沟槽下方的隔离区域中。 每个第二沟槽比相应的第一沟槽更窄和更深。 第一氧化物层形成在每个第二沟槽的侧壁和底表面上。 第一沟槽填充有绝缘层。

公开(公告)号：US20080102579A1

公开(公告)日：2008-05-01

申请号：US11617690

申请日：2006-12-28

申请人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 间隔件形成在每个第一沟槽的侧壁上。 第二沟槽形成在对应的第一沟槽下方的隔离区域中。 每个第二沟槽比相应的第一沟槽更窄和更深。 第一氧化物层形成在每个第二沟槽的侧壁和底表面上。 第一沟槽填充有绝缘层。

公开(公告)号：US08343846B2

公开(公告)日：2013-01-01

申请号：US12131229

申请日：2008-06-02

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer.

摘要翻译： 一种在半导体器件中形成隔离层的方法，包括：利用隔离掩模通过蚀刻在半导体衬底的隔离区上形成沟槽; 在沟槽的下部形成第一绝缘层; 在包括第一绝缘层的半导体衬底上形成第二绝缘层; 蚀刻第二绝缘层以增加隔离区上的纵横比; 以及在所述第二绝缘层的周边区域上形成第三绝缘层，以用所述第三绝缘层填充形成在所述第二绝缘层上的护城河。

公开(公告)号：US07932159B2

公开(公告)日：2011-04-26

申请号：US12943578

申请日：2010-11-10

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers.

摘要翻译： 闪存器件及其制造方法技术领域本发明涉及闪速存储器件及其制造方法。 在本发明的一个方面，闪存器件包括形成在半导体衬底中并且在其下部具有台阶的沟槽，形成在半导体衬底的有源区中的隧道绝缘层，形成在隧道绝缘层上的第一导电层 沟槽和第一导电层之间的隔离层间隙填充，以及形成在第一导电层上并具有与隔离层部分重叠的一侧的第二导电层。

公开(公告)号：US20090170282A1

公开(公告)日：2009-07-02

申请号：US12131229

申请日：2008-06-02

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer.

摘要翻译： 一种在半导体器件中形成隔离层的方法，包括：利用隔离掩模通过蚀刻在半导体衬底的隔离区上形成沟槽; 在沟槽的下部形成第一绝缘层; 在包括第一绝缘层的半导体衬底上形成第二绝缘层; 蚀刻第二绝缘层以增加隔离区上的纵横比; 以及在所述第二绝缘层的周边区域上形成第三绝缘层，以用所述第三绝缘层填充形成在所述第二绝缘层上的护城河。

公开(公告)号：US06900096B2

公开(公告)日：2005-05-31

申请号：US10285590

申请日：2002-11-01

申请人： Cha Deok Dong ,  Sang Wook Park

发明人： Cha Deok Dong ,  Sang Wook Park

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28273

摘要： The present invention relates to a method of manufacturing a flash memory cell capable of preventing an oxidation of a dielectric film between a floating gate and a control gate, in a manner that a polysilicon film for floating gate is deposited, nitrogen ions are injected to make amorphous and contaminate the surface of the polysilicon film.

摘要翻译： 本发明涉及一种制造闪存单元的方法，该闪速存储单元能够防止浮置栅极和控制栅极之间的电介质膜氧化，从而沉积浮栅的多晶硅膜，注入氮离子以形成 无定形并污染多晶硅膜的表面。

公开(公告)号：US06849519B2

公开(公告)日：2005-02-01

申请号：US10611500

申请日：2003-07-01

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/762

CPC分类号： H01L21/76213 ,  H01L21/76205 ,  H01L21/76235

摘要： A method of forming an isolation layer in semiconductor devices is disclosed. The method includes forming the isolating film by means of a method in which a method of forming a V-type trench at the isolation region, implanting ions capable of accelerating oxidization action into the center portion of the V-type trench, implementing an oxidization process to form an insulating film consisting of an oxide film at the isolation region, and then completely burying the trench with an insulating material, using the LOCOS method, and a method of forming a trench type isolation layer, are applied together. Therefore, as the top corner of the trench is formed with an inclination, and a concentration of the electric field and a formation of a moat can be simultaneously prevented.

摘要翻译： 公开了一种在半导体器件中形成隔离层的方法。 该方法包括通过以下方法形成隔离膜：其中在隔离区域形成V型沟槽的方法，将能够加速氧化作用的离子注入到V型沟槽的中心部分中，实现氧化过程 在隔离区域形成由氧化物膜构成的绝缘膜，然后使用LOCOS方法和形成沟槽型隔离层的方法将绝缘材料完全埋入沟槽中。 因此，由于沟槽的顶角形成倾斜，并且可以同时防止电场的集中和护城河的形成。

公开(公告)号：US06777348B2

公开(公告)日：2004-08-17

申请号：US10631362

申请日：2003-07-31

申请人： Seung Woo Shin ,  Cha Deok Dong

发明人： Seung Woo Shin ,  Cha Deok Dong

IPC分类号： H01L2131

CPC分类号： H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31662

摘要： Disclosed is a method of forming an oxynitride film. The method comprises the steps of loading a silicon substrate into an oxidization furnace, implanting an oxygen based source gas into the oxidization furnace to grow a pure silicon oxide film on the silicon substrate, blocking implantation of the oxygen based source gas and implanting an inert gas to exhaust the oxygen based source gas remaining within the oxidization furnace, raising a temperature within the oxidization furnace to a nitrification process temperature, stabilizing the temperature within the oxidization furnace, implementing a nitrification process for the pure silicon oxide film by implanting a nitrogen based source gas, and stopping implantation of the nitrogen based source gas and rapidly cooling the oxidization furnace while implanting the inert gas into the oxidization furnace.

摘要翻译： 公开了形成氮氧化物膜的方法。 该方法包括以下步骤：将硅衬底装载到氧化炉中，将氧基源气体注入到氧化炉中以在硅衬底上生长纯氧化硅膜，阻止氧基源气体的注入和注入惰性气体 排出残留在氧化炉内的氧气源气体，将氧化炉内的温度升高至硝化处理温度，稳定氧化炉内的温度，通过注入氮源，实施纯氧化硅膜的硝化处理 气体，并停止氮源气体的注入，并在将惰性气体注入氧化炉的同时快速冷却氧化炉。

公开(公告)号：US20110059594A1

公开(公告)日：2011-03-10

申请号：US12943578

申请日：2010-11-10

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers.

摘要翻译： 闪存器件及其制造方法技术领域本发明涉及闪速存储器件及其制造方法。 在本发明的一个方面，闪存器件包括形成在半导体衬底中并且在其下部具有台阶的沟槽，形成在半导体衬底的有源区中的隧道绝缘层，形成在隧道绝缘层上的第一导电层 沟槽和第一导电层之间的隔离层间隙填充，以及形成在第一导电层上并具有与隔离层部分重叠的一侧的第二导电层。