公开(公告)号：US20140151816A1

公开(公告)日：2014-06-05

申请号：US13689979

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66969

Abstract: One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region.

Abstract translation: 一个器件包括形成在半导体衬底中的第一和第二间隔开的有源区，位于第一有源区上的栅极绝缘材料层，和具有位于栅绝缘材料上方的第一部分的导线特征，以及第二部分 导电地接触第二活性区域。 一种方法包括在半导体衬底中形成第一和第二间隔开的有源区，在第一和第二有源区上形成栅极绝缘材料层，执行蚀刻工艺以去除形成在第二有源区上的栅极绝缘材料的一部分 区域以暴露第二有源区域的一部分，以及形成导线特征，其包括位于形成在第一有源区上的栅绝缘材料层之上的第一部分和与第二有源区的暴露部分导电接触的第二部分 地区。