公开(公告)号：US20180240796A1

公开(公告)日：2018-08-23

申请号：US15890452

申请日：2018-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Frank Jakubowski

IPC: H01L27/06 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/84 ,  H01L21/762 ,  H01L49/02 ,  H01L29/49 ,  H01L23/31 ,  H01L29/417 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/76283 ,  H01L21/84 ,  H01L23/3178 ,  H01L23/535 ,  H01L27/108 ,  H01L27/1203 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/495

Abstract: A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.

公开(公告)号：US09299616B1

公开(公告)日：2016-03-29

申请号：US14527867

申请日：2014-10-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/11 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L21/823437 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28061 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628

Abstract: Integrated circuits employing replacement metal gate technologies with separate workfunction material layers and raised source/drain structures and methods for fabricating the same are disclosed herein. In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a first workfunction material layer over an ILD layer, along the sidewall spacer structures, and over the high-k material layer. The method further includes forming a masking layer over the first workfunction material layer, performing a tilted ion implant wherein ions are implanted at the masking layer over the ILD layer and along the sidewall spacer structures, selectively etching the masking layer and the first workfunction material from over the ILD layer and from along the sidewall spacer structures, and forming a second workfunction material layer over the ILD layer, along the sidewall spacer structures, and over the first workfunction material layer.

Abstract translation: 本文公开了采用具有单独的功函数材料层的替代金属栅极技术的集成电路和升高的源极/漏极结构及其制造方法。 在一个示例性实施例中，制造集成电路的方法包括在ILD层上沿着侧壁间隔结构以及在高k材料层上形成第一功函数材料层。 该方法还包括在第一功函数材料层上形成掩模层，执行倾斜离子注入，其中离子注入到ILD层上的屏蔽层上并沿着侧壁间隔结构，选择性地蚀刻掩模层和第一功函数材料 在ILD层上并沿着侧壁间隔结构，并且沿ILD层，沿着侧壁间隔结构以及在第一功函数材料层上方形成第二功函数材料层。

公开(公告)号：US20140159125A1

公开(公告)日：2014-06-12

申请号：US13710575

申请日：2012-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L29/417 ,  H01L29/40

CPC classification number: H01L24/03 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/37001 ,  H01L2924/00

Abstract: One device herein includes first and second spaced-apart active regions, a transistor formed in and above the first active region, wherein the transistor has a gate electrode, a conductive contact landing pad that is coupled to the second active region, wherein the contact landing pad is made of the same conductive material as the gate electrode, and a contact that is coupled to the contact landing pad. One method herein includes forming first and second spaced-apart active regions, forming a layer of gate insulation material on the active regions, performing an etching process to remove the gate insulation material formed on the second active region, performing a common process operation to form a gate electrode structure above the gate insulation material on the first active region and the contact landing pad that is conductively coupled to the second active region and forming a contact to the contact landing pad.

Abstract translation: 本文中的一个器件包括第一和第二间隔开的有源区，形成在第一有源区中和之上的晶体管，其中晶体管具有栅电极，耦合到第二有源区的导电接触着陆焊盘，其中接触着地 焊盘由与栅极电极相同的导电材料制成，以及耦合到触点着陆焊盘的触点。 这里的一种方法包括形成第一和第二间隔开的有源区域，在有源区域上形成栅极绝缘材料层，执行蚀刻工艺以去除形成在第二有源区域上的栅极绝缘材料，执行共同的工艺操作以形成 位于第一有源区上的栅极绝缘材料上方的栅极电极结构和与第二有源区导电耦合并形成与接触着陆焊盘接触的触点接合焊盘。

公开(公告)号：US20170317097A1

公开(公告)日：2017-11-02

申请号：US15653661

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/11568 ,  H01L29/423 ,  H01L27/12 ,  H01L27/11521 ,  H01L21/762 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/1207 ,  H01L28/00 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42336 ,  H01L29/42352

Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US09324854B2

公开(公告)日：2016-04-26

申请号：US14226176

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

IPC: H01L29/772 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L21/285 ,  H01L21/288 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions.

Abstract translation: 半导体器件包括位于有源区上方的高k金属栅电极结构，具有位于栅极高度的顶表面，并且包括高k电介质材料和电极金属。 引出的漏极和源极区域横向邻近高k金属栅极电极结构定位并连接到有源区域，并且每个升高的漏极和源极区域的顶表面位于栅极下方的接触高度水平处 身高。 蚀刻停止层位于凸起的漏极和源极区域的顶表面上方，并且接触元件连接到凸起的漏极和源极区域之一，接触元件延伸穿过蚀刻停止层， k金属栅极电极结构和升高的漏极和源极区域。

公开(公告)号：US10466126B2

公开(公告)日：2019-11-05

申请号：US15906368

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: G01L9/00 ,  B81B3/00 ,  B81C1/00

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to pressure sensors and methods of manufacture. The structure includes: a top membrane of semiconductor material having edges defined by epitaxial material and a liner material; a back gate under the top membrane; and a cavity defined between the top membrane and the back gate.

公开(公告)号：US10056369B1

公开(公告)日：2018-08-21

申请号：US15890452

申请日：2018-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Frank Jakubowski

IPC: H01L21/00 ,  H01L27/06 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/84 ,  H01L21/762 ,  H01L49/02 ,  H01L29/49 ,  H01L23/31 ,  H01L29/417 ,  H01L23/535 ,  H01L29/06 ,  H01L27/12 ,  H01L27/108

Abstract: A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.

公开(公告)号：US09748259B1

公开(公告)日：2017-08-29

申请号：US15053485

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/11568 ,  H01L21/762 ,  H01L21/28 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/265 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/1207 ,  H01L28/00 ,  H01L29/42336 ,  H01L29/42352

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US09064733B2

公开(公告)日：2015-06-23

申请号：US14590076

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L29/66 ,  H01L27/11 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/1104 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66969

Abstract: A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.

Abstract translation: 器件包括位于半导体衬底中的第一和第二间隔开的有源区，位于第一和第二间隔开的有源区之间的隔离区和位于第一有源区上的栅极绝缘材料层。 第一导线特征从第一有源区连续延伸并跨越隔离区到第二有源区，其中第一导线特征包括位于第一有源区上的栅极绝缘材料层正上方的第一部分， 以及与第二有源区域导电接触的第二部分。

公开(公告)号：US20180175209A1

公开(公告)日：2018-06-21

申请号：US15384706

申请日：2016-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/3105 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor structure includes a support substrate including a semiconductor material, a buried insulation layer positioned above the support substrate, a semiconductor layer positioned above the buried insulation layer, the semiconductor layer having an upper surface and a lower surface, the lower surface being positioned on the buried insulation layer, and at least one nonvolatile memory cell. The nonvolatile memory cell includes a channel region, a front gate structure, a doped back gate region and a charge storage material. The channel region is located in the semiconductor layer. The front gate structure is located above the channel region and the upper surface of the semiconductor layer. The doped back gate region is located in the support substrate below the channel region. The charge storage material is embedded at least into a portion of the buried insulation layer between the channel region and the back gate region.