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    Method for compensating for temperature effects in semiconductor device structures using a diode structure and a tunable resistor
    1.
    发明授权
    Method for compensating for temperature effects in semiconductor device structures using a diode structure and a tunable resistor 有权

    公开(公告)号：US10026753B2

    公开(公告)日：2018-07-17

    申请号：US15799243

    申请日：2017-10-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Juergen Faul

    IPC: H01L27/12 ,  H01L27/02 ,  H01L23/50

    Abstract: A method includes providing a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region. A semiconductor device is provided in the SOI region. The semiconductor device includes a gate structure, a diode structure provided in the hybrid region and coupled to a substrate material of the SOI region, a supply circuit arrangement including first and second supply lines, a first resistor coupled between the first supply line and a first terminal of the diode structure, and a second resistor coupled between the second supply line and the substrate material positioned beneath the gate structure. At least one of the first and second resistors comprises a tunable resistor. A resistance of the tunable resistor is adjusted so as to adjust a threshold voltage (Vt) of the semiconductor device in dependence on an operating temperature of the SOI region.

    TUNABLE CAPACITOR FOR FDSOI APPLICATIONS
    2.
    发明申请
    TUNABLE CAPACITOR FOR FDSOI APPLICATIONS 有权
    用于FDSOI应用的电容电容器

    公开(公告)号：US20160379993A1

    公开(公告)日：2016-12-29

    申请号：US14750236

    申请日：2015-06-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Juergen Faul

    IPC: H01L27/12 ,  H01L21/84 ,  H01L29/93

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/93

    Abstract: The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material, a gate structure formed on the active semiconductor layer, and a back gate region provided in the base substrate material below the gate structure opposing the gate structure. Herein, the back gate region may be electrically insulated from the surrounding base substrate material via an isolation region surrounding the back gate region.

    Abstract translation: 本公开一方面提供了一种半导体器件，其包括：SOI衬底，其具有设置在掩埋绝缘材料层上的有源半导体层，所述有源半导体层又形成在基底衬底材料上，形成在有源半导体层上的栅极结构， 以及设置在与栅极结构相对的栅极结构下方的基底衬底材料中的背栅极区域。 这里，背栅区域可以通过围绕背栅区域的隔离区域与周围的基底材料电绝缘。

    Integrated circuits with separate workfunction material layers and methods for fabricating the same
    3.
    发明授权
    Integrated circuits with separate workfunction material layers and methods for fabricating the same 有权
    具有单独的功函数材料层的集成电路及其制造方法

    公开(公告)号：US09299616B1

    公开(公告)日：2016-03-29

    申请号：US14527867

    申请日：2014-10-30

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Juergen Faul ,  Frank Jakubowski

    IPC: H01L27/11 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423

    CPC classification number: H01L21/823437 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28061 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628

    Abstract: Integrated circuits employing replacement metal gate technologies with separate workfunction material layers and raised source/drain structures and methods for fabricating the same are disclosed herein. In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a first workfunction material layer over an ILD layer, along the sidewall spacer structures, and over the high-k material layer. The method further includes forming a masking layer over the first workfunction material layer, performing a tilted ion implant wherein ions are implanted at the masking layer over the ILD layer and along the sidewall spacer structures, selectively etching the masking layer and the first workfunction material from over the ILD layer and from along the sidewall spacer structures, and forming a second workfunction material layer over the ILD layer, along the sidewall spacer structures, and over the first workfunction material layer.

    Abstract translation: 本文公开了采用具有单独的功函数材料层的替代金属栅极技术的集成电路和升高的源极/漏极结构及其制造方法。 在一个示例性实施例中，制造集成电路的方法包括在ILD层上沿着侧壁间隔结构以及在高k材料层上形成第一功函数材料层。 该方法还包括在第一功函数材料层上形成掩模层，执行倾斜离子注入，其中离子注入到ILD层上的屏蔽层上并沿着侧壁间隔结构，选择性地蚀刻掩模层和第一功函数材料 在ILD层上并沿着侧壁间隔结构，并且沿ILD层，沿着侧壁间隔结构以及在第一功函数材料层上方形成第二功函数材料层。

    LOW LEAKAGE PMOS TRANSISTOR
    5.
    发明申请
    LOW LEAKAGE PMOS TRANSISTOR 审中-公开
    低漏电PMOS晶体管

    公开(公告)号：US20150214116A1

    公开(公告)日：2015-07-30

    申请号：US14165107

    申请日：2014-01-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Peter Javorka ,  Juergen Faul ,  Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter

    IPC: H01L21/8238 ,  H01L21/266 ,  H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L21/324 ,  H01L21/02

    CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848

    Abstract: A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices.

    Abstract translation: 提供一种形成半导体器件的方法，包括以下步骤：形成第一和第二PMOS晶体管器件，其中第一PMOS晶体管器件为低标准或高电压阈值晶体管器件，而第二PMOS晶体管器件为超高电压阈值晶体管器件 并且其中形成所述第一PMOS晶体管器件包括注入掺杂剂以形成所述第一PMOS晶体管器件的源极和漏极结，并且在注入所述掺杂剂之后执行所述第一PMOS晶体管器件的热退火，以及形成所述第二PMOS晶体管器件包括注入掺杂剂 以在第一PMOS晶体管器件进行热退火之后形成第二PMOS晶体管器件的源极和漏极结。

    CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
    6.
    发明申请
    CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME 有权
    接触半导体器件的接地垫及其制造方法

    公开(公告)号：US20140159125A1

    公开(公告)日：2014-06-12

    申请号：US13710575

    申请日：2012-12-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Frank Jakubowski ,  Juergen Faul

    IPC: H01L29/417 ,  H01L29/40

    CPC classification number: H01L24/03 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2224/034 ,  H01L2224/03614 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/37001 ,  H01L2924/00

    Abstract: One device herein includes first and second spaced-apart active regions, a transistor formed in and above the first active region, wherein the transistor has a gate electrode, a conductive contact landing pad that is coupled to the second active region, wherein the contact landing pad is made of the same conductive material as the gate electrode, and a contact that is coupled to the contact landing pad. One method herein includes forming first and second spaced-apart active regions, forming a layer of gate insulation material on the active regions, performing an etching process to remove the gate insulation material formed on the second active region, performing a common process operation to form a gate electrode structure above the gate insulation material on the first active region and the contact landing pad that is conductively coupled to the second active region and forming a contact to the contact landing pad.

    Abstract translation: 本文中的一个器件包括第一和第二间隔开的有源区，形成在第一有源区中和之上的晶体管，其中晶体管具有栅电极，耦合到第二有源区的导电接触着陆焊盘，其中接触着地 焊盘由与栅极电极相同的导电材料制成，以及耦合到触点着陆焊盘的触点。 这里的一种方法包括形成第一和第二间隔开的有源区域，在有源区域上形成栅极绝缘材料层，执行蚀刻工艺以去除形成在第二有源区域上的栅极绝缘材料，执行共同的工艺操作以形成 位于第一有源区上的栅极绝缘材料上方的栅极电极结构和与第二有源区导电耦合并形成与接触着陆焊盘接触的触点接合焊盘。

    Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
    7.
    发明授权
    Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same 有权

    公开(公告)号：US09917087B2

    公开(公告)日：2018-03-13

    申请号：US13961554

    申请日：2013-08-07

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Stefan Flachowksy ,  Juergen Faul ,  Jan Hoentschel

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L27/092 ,  H01L21/823807

    Abstract: Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.

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