公开(公告)号：US11056430B1

公开(公告)日：2021-07-06

申请号：US16813835

申请日：2020-03-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chengang Feng ,  Handoko Linewih ,  Yanxia Shao ,  Yudi Setiawan

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L49/02 ,  H01L23/528

Abstract: According to various embodiments, a semiconductor device may include a thin film arranged within a first inter-level dielectric layer, a masking region, and a contact plug. The masking region may be arranged over the thin film, within the first inter-level dielectric layer. The masking region may be structured to have a higher etch rate than the first inter-level dielectric layer. The contact plug may extend along a vertical axis, from a second inter-level dielectric layer to the thin film. A bottom portion of the contact plug may be surrounded by the masking region. The bottom portion of the contact plug may include a lateral member that extends along a horizontal plane at least substantially perpendicular to the vertical axis. The lateral member may be in contact with the thin film.

公开(公告)号：US10651166B2

公开(公告)日：2020-05-12

申请号：US15609566

申请日：2017-05-31

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Handoko Linewih ,  Chien-Hsin Lee

IPC: H01L27/02 ,  H01L23/525 ,  H01L27/06

Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.

公开(公告)号：US09870939B2

公开(公告)日：2018-01-16

申请号：US14838375

申请日：2015-08-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Handoko Linewih ,  Ming Li ,  Sevashanmugam Marimuthu ,  Ronghua Yu

IPC: H02H3/22 ,  H01L21/762 ,  H02H9/04 ,  H01L27/06 ,  H01L29/10 ,  H01L27/02

CPC classification number: H01L21/76224 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/1095 ,  H02H9/04

Abstract: Devices and methods of forming an integrated circuit (IC) that offer protection against ESD in high voltage (HV) circuit applications are disclosed. A device includes N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, where N is an integer greater than 1. A first pad of the device is coupled to a first FET and a second pad is coupled to an Nth FET. The device also includes a stacked/distributed RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an ESD event. During the ESD event, the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET by turning them on using parasitic conduction to cause the short circuit.