公开(公告)号：US09772852B2

公开(公告)日：2017-09-26

申请号：US14694815

申请日：2015-04-23

Applicant: Google Inc.

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein ,  Qiuling Zhu

IPC: G06F9/38 ,  G06T1/20

CPC classification number: G06F9/3802 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30134 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3871 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8023 ,  G06T1/20 ,  H04N3/14 ,  H04N3/1575

Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

公开(公告)号：US20170257515A1

公开(公告)日：2017-09-07

申请号：US15598933

申请日：2017-05-18

Applicant: Google Inc.

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Qiuling Zhu ,  Daniel Frederic Finchelstein

IPC: H04N1/32 ,  B41F15/08 ,  G06T1/60

CPC classification number: H04N1/32101 ,  B41F15/0804 ,  G06T1/60

Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.

公开(公告)号：US20170256230A1

公开(公告)日：2017-09-07

申请号：US15599086

申请日：2017-05-18

Applicant: Google Inc.

Inventor： Albert Meixner ,  Neeti Desai ,  Dilan Manatunga ,  Jason Rupert Redgrave ,  William Mark

IPC: G09G5/00 ,  G06T1/20 ,  G09G5/02

CPC classification number: G09G5/006 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28 ,  G09G5/02 ,  G09G2340/02 ,  H04N1/32358 ,  H04N2201/3291

Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.

公开(公告)号：US20170242943A1

公开(公告)日：2017-08-24

申请号：US15591984

申请日：2017-05-10

Applicant: Google Inc.

Inventor： Albert Meixner ,  Ofer Shacham ,  David Patterson ,  Daniel Frederic Finchelstein ,  Qiuling Zhu ,  Jason Rupert Redgrave

IPC: G06F17/50 ,  G06T1/20 ,  G06F9/30

CPC classification number: G06F8/20 ,  G06F8/10 ,  G06F9/3004 ,  G06F9/30101 ,  G06F17/5009 ,  G06T1/20 ,  G06T2200/28

Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

公开(公告)号：US20160314555A1

公开(公告)日：2016-10-27

申请号：US14694828

申请日：2015-04-23

Applicant: Google Inc.

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Albert Meixner ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  David Patterson ,  Neeti Desai ,  Donald Stark ,  Edward T. Chang ,  William R. Mark

IPC: G06T1/20 ,  G06T1/60 ,  H04N5/91 ,  H04N5/378

CPC classification number: G06T1/20 ,  G06T1/60 ,  H04N5/378 ,  H04N5/91

Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.

Abstract translation: 描述了一种装置。 该装置包括图像处理单元。 图像处理单元包括网络。 图像处理单元包括多个模板处理器电路，每个模板处理器电路各自包括耦合到二维移位寄存器阵列结构的执行单元通道的阵列，以通过执行程序代码来同时处理多个重叠模版。 图像处理单元包括分别耦合在多个模板处理器和网络之间的多个片材生成器。 片材生成器将图像数据的输入线组分解成图像数据的输入片以供模板处理器处理，并且从从模版处理器接收的图像数据的输出片材中形成图像数据的输出线组。 图像处理单元包括耦合到网络的多个行缓冲单元，以在从生成模板处理器到消耗模板处理器的方向上传递线组，以实现整个程序流程。

公开(公告)号：US20160313980A1

公开(公告)日：2016-10-27

申请号：US14694890

申请日：2015-04-23

Applicant: Google Inc.

Inventor： Albert Meixner ,  Ofer Shacham ,  David Patterson ,  Daniel Frederic Finchelstein ,  Qiuling Zhu ,  Jason Rupert Redgrave

IPC: G06F9/44 ,  G06F9/30

CPC classification number: G06F17/5009 ,  G06F8/10 ,  G06F8/20 ,  G06F9/3004 ,  G06F9/30101 ,  G06T1/20 ,  G06T2200/28

Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

Abstract translation: 描述了一种方法，其包括在应用软件开发环境内实例化具有预期存储器的第一和第二区域的指令集架构和存储器模型的虚拟处理器。 第一个保留区域是保留输入图像数组的数据。 第二保留区域是保留输出图像数组的数据。 该方法还包括通过自动地针对第一保留区域来模拟指令集架构的存储器加载指令的执行，并且相对于虚拟处理器在正交坐标系中的位置识别具有第一和第二坐标的期望输入数据并以指令格式表示 的存储器加载指令。