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    Synchronized data chaining using on-chip cache
    22.
    发明授权
    Synchronized data chaining using on-chip cache 有权

    公开(公告)号：US11830102B2

    公开(公告)日：2023-11-28

    申请号：US17943047

    申请日：2022-09-12

    Applicant: Google LLC

    Inventor： Benjamin Dodge ,  Jason Rupert Redgrave ,  Xiaoyu Ma

    IPC: G06T1/20 ,  G06T1/60 ,  G06F13/28 ,  G06F15/78

    CPC classification number: G06T1/20 ,  G06F13/28 ,  G06F15/7825 ,  G06T1/60

    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.

    Compiler managed memory for image processor
    27.
    发明授权
    Compiler managed memory for image processor 有权

    公开(公告)号：US10685422B2

    公开(公告)日：2020-06-16

    申请号：US16272819

    申请日：2019-02-11

    Applicant: Google LLC

    Inventor： Albert Meixner ,  Hyunchul Park ,  Qiuling Zhu ,  Jason Rupert Redgrave

    IPC: G09G3/36 ,  G06T1/60 ,  G06F9/38 ,  G06T1/20 ,  G06F9/30

    Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.

    VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS
    29.
    发明申请
    VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS 审中-公开

    公开(公告)号：US20200120287A1

    公开(公告)日：2020-04-16

    申请号：US16659702

    申请日：2019-10-22

    Applicant: Google LLC

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

    IPC: H04N5/262 ,  G06T1/20 ,  G06T1/60

    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

    Shift register with reduced wiring complexity
    30.
    发明授权
    Shift register with reduced wiring complexity 有权

    公开(公告)号：US10477164B2

    公开(公告)日：2019-11-12

    申请号：US15595403

    申请日：2017-05-15

    Applicant: Google LLC

    Inventor： Jason Rupert Redgrave

    IPC: H04N9/04 ,  G06T1/20 ,  G11C19/38 ,  H04N5/907 ,  G06F15/173 ,  G06F15/80 ,  G11C7/10 ,  H01P5/12 ,  H03K19/177 ,  G11C19/00 ,  G11C19/28

    Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

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