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公开(公告)号：US20160219225A1
公开(公告)日：2016-07-28
申请号：US14603354
申请日：2015-01-22
Applicant: GOOGLE INC.
Inventor： Qiuling Zhu , Ofer Shacham , Jason Rupert Redgrave , Daniel Frederic Finchelstein , Albert Meixner
IPC: H04N5/262
Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
Abstract translation: 在一般方面，一种装置可以包括图像处理逻辑（IPL），被配置为对与具有W像素的宽度和H像素的高度的图像相对应的像素数据执行图像处理操作，以在垂直切片中产生输出像素数据 K个像素，使用S×S像素的K个垂直重叠的模板，K大于1且小于H，S大于或等于2，并且W大于S.该装置还可以包括线缓冲器，其操作上与 IPL，线缓冲器被配置为缓冲IPL的像素数据。 线缓冲器可以包括宽度为W且高度为（S-1）的全尺寸缓冲器。 线缓冲器还可以包括具有SB的宽度和K的高度的滑动缓冲器，SB大于或等于S且小于W.
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Patent Agency Ranking
公开(公告)号：US09830150B2
公开(公告)日：2017-11-28
申请号：US14960334
申请日：2015-12-04
Applicant: Google Inc.
Inventor： Artem Vasilyev , Jason Rupert Redgrave , Albert Meixner , Ofer Shacham
CPC classification number: G06F9/3001 , G06F7/57 , G06F9/30014 , G06F15/80
Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.
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23.发明申请公开(公告)号：US20170287103A1
公开(公告)日：2017-10-05
申请号：US15628480
申请日：2017-06-20
Applicant: Google Inc.
Inventor： Albert Meixner , Hyunchul Park , William R. Mark , Daniel Frederic Finchelstein , Ofer Shacham
CPC classification number: G06T1/20 , G06F8/447 , G06F9/5077
Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for restructuring an image processing pipeline. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; or splitting the directed acyclic graph into smaller graphs.
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公开(公告)号：US09769356B2
公开(公告)日：2017-09-19
申请号：US14694750
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Ofer Shacham , Jason Rupert Redgrave , Albert Meixner , Qiuling Zhu , Daniel Frederic Finchelstein , David Patterson , Donald Stark
CPC classification number: H04N3/1575 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30134 , G06T1/60
Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
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公开(公告)号：US20170257585A1
公开(公告)日：2017-09-07
申请号：US15598027
申请日：2017-05-17
Applicant: Google Inc.
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
CPC classification number: H04N5/3692 , G06T1/60 , H04N5/91
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
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公开(公告)号：US20160316107A1
公开(公告)日：2016-10-27
申请号：US14694750
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Ofer Shacham , Jason Rupert Redgrave , Albert Meixner , Qiuling Zhu , Daniel Frederic Finchelstein , David Patterson , Donald Stark
IPC: H04N3/14
CPC classification number: H04N3/1575 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30134 , G06T1/60
Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
Abstract translation: 描述了一种装置。 该装置包括耦合到二维移位寄存器阵列结构的执行通道阵列。 执行通道阵列中的位置耦合到二维移位寄存器阵列结构中的相同位置，使得不同的执行通道具有不同的专用寄存器。
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