公开(公告)号：US20100235576A1

公开(公告)日：2010-09-16

申请号：US12336048

申请日：2008-12-16

申请人： Guy L. Guthrie ,  Alvan W. Ng ,  Michael S. Siegel ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

发明人： Guy L. Guthrie ,  Alvan W. Ng ,  Michael S. Siegel ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/0811 ,  G06F12/0862

摘要： A victim cache memory includes a cache array, a cache directory of contents of the cache array, and a cache controller that controls operation of the victim cache memory. The cache controller, responsive to receiving a castout command identifying a victim cache line castout from another cache memory, causes the victim cache line to be held in the cache array. If the other cache memory is a higher level cache in the cache hierarchy of the processor core, the cache controller marks the victim cache line in the cache directory so that it is less likely to be evicted by a replacement policy of the victim cache, and otherwise, marks the victim cache line in the cache directory so that it is more likely to be evicted by the replacement policy of the victim cache.

摘要翻译： 受害者缓存存储器包括缓存阵列，高速缓存阵列的内容的高速缓存目录以及控制受害者缓存存储器的操作的高速缓存控制器。 高速缓存控制器响应于从另一高速缓冲存储器接收识别受害者高速缓存线路突发的丢弃命令，使受害者高速缓存行保持在高速缓存阵列中。 如果其他高速缓冲存储器是处理器核心的高速缓存层级中的较高级缓存，则高速缓存控制器将高速缓存目录中的受害者高速缓存行标记为不太可能被受害缓存的替换策略驱逐， 否则，将缓存目录中的受害者缓存行标记为更有可能被受害者缓存的替换策略驱逐。

公开(公告)号：US20100153647A1

公开(公告)日：2010-06-17

申请号：US12335975

申请日：2008-12-16

申请人： Guy L. Guthrie ,  Alvan W. Ng ,  Michael S. Siegel ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

发明人： Guy L. Guthrie ,  Alvan W. Ng ,  Michael S. Siegel ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0862

摘要： A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

摘要翻译： 数据处理系统包括由互连结构耦合的第一处理单元和第二处理单元。 第一处理单元具有第一处理器核心和相关联的第一上部和第一下层高速缓存，并且第二处理单元具有第二处理器核心和相关联的第二上部和下部高速缓存。 响应于数据请求，选择受害者高速缓存行用于从第一较低级别缓存进行舍弃。 第一处理单元在互连结构上发出横向聚合（LCO）命令，该命令标识要从第一较低级缓存中抛出的受害缓存行，并且指示较低级缓存是预期目的地。 响应于指示LCO命令的成功的一致性响应，从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。

公开(公告)号：US07716428B2

公开(公告)日：2010-05-11

申请号：US11364774

申请日：2006-02-28

申请人： Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping a data-invalid state update request, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and that a memory block associated with the address tag is likely cached within the first coherency domain.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态， 存储位置不包含有效数据。 响应于窥探数据无效状态更新请求，第一缓存存储器将相关性状态字段从第一数据无效一致性状态更新为指示地址标签有效的第二数据无效一致性状态，存储位置 不包含有效数据，并且与地址标签相关联的存储器块可能被缓存在第一个相干域内。

公开(公告)号：US07689771B2

公开(公告)日：2010-03-30

申请号：US11532981

申请日：2006-09-19

申请人： James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0804 ,  G06F12/0815

摘要： According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.

摘要翻译： 根据一个实施例，一种数据处理系统中的一致性管理方法包括：将高速缓存行以独占所有权一致性状态保存在上级高速缓冲存储器中，之后从高级缓存存储器中移除高速缓存行， 从高级缓存存储器到高级缓存的高速缓存行。 丢弃请求包括共享所有权一致性状态的指示。 响应于抛出请求，高速缓存行以根据转储请求确定的一致性状态被放置在较低级高速缓冲存储器中。

公开(公告)号：US07523268B2

公开(公告)日：2009-04-21

申请号：US12114790

申请日：2008-05-04

申请人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。 输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。 失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。 调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。 通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

公开(公告)号：US07475195B2

公开(公告)日：2009-01-06

申请号：US11136651

申请日：2005-05-24

申请人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Leo J. Clark ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0822

摘要： Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency response to said domain reset request is received. In response to said coherency response indicating that said target memory block is not cached in said remote coherency domain, a domain indication of said local coherency domain is updated to indicate that said target memory block is cached, if at all, only within said local coherency domain.

摘要翻译： 本地一致性域中的擦除逻辑向远程一致性域中的至少一个高速缓存层次结构发出一个域重置请求，该请求强制所保存在所述远程一致性域中的目标存储器块的任何高速缓存副本的无效。 接收到对所述域重置请求的一致性响应。 响应于所述相关性响应指示所述目标存储器块未被高速缓存在所述远程一致性域中，所述本地一致性域的域指示被更新以指示所述目标存储器块被缓存，如果完全只在所述局部一致性内 域。

公开(公告)号：US20080215824A1

公开(公告)日：2008-09-04

申请号：US12106102

申请日：2008-04-18

申请人： BENJIMAN L. GOODMAN ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： BENJIMAN L. GOODMAN ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.

摘要翻译： 高速缓存一致数据处理系统至少包括支持第一处理单元的第一高速缓冲存储器和支持第二处理单元的第二高速缓冲存储器。 第一缓存存储器包括缓存阵列和高速缓存阵列的内容的高速缓存目录。 响应于第一高速缓冲存储器在互连上检测指定请求地址的广播操作，第一高速缓冲存储器从操作中确定与请求地址相关联的操作类型和一致性状态。 响应于确定类型和一致性状态，第一高速缓存存储器过滤掉广播操作而不访问高速缓存目录。

公开(公告)号：US09619390B2

公开(公告)日：2017-04-11

申请号：US12649548

申请日：2009-12-30

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/02 ,  G06F12/0862 ,  G06F12/0815

CPC分类号： G06F12/0862 ,  G06F12/0815

摘要： According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.

公开(公告)号：US09176876B2

公开(公告)日：2015-11-03

申请号：US13445646

申请日：2012-04-12

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0811 ,  G06F12/12

摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

公开(公告)号：US08856455B2

公开(公告)日：2014-10-07

申请号：US13433022

申请日：2012-03-28

申请人： Sanjeev Ghai ,  Guy L. Guthrie ,  William J. Starke ,  Jeff A. Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

发明人： Sanjeev Ghai ,  Guy L. Guthrie ,  William J. Starke ,  Jeff A. Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0897 ,  G06F12/126

摘要： A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.

摘要翻译： 数据处理系统包括由上层和下层高速缓存支持的处理器核心。 响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。 响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。 为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存 线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。