公开(公告)号：US08363484B2

公开(公告)日：2013-01-29

申请号：US13064189

申请日：2011-03-09

申请人： Vikas Chandra ,  Daeyeon Kim

发明人： Vikas Chandra ,  Daeyeon Kim

IPC分类号： G11C7/10

CPC分类号： G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  G11C11/418

摘要： A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse width of the asserted write word line signal is dependent on time taken by the addressed memory cells to store the write data, thereby leading to a significant reduction in the size of the pulse width when compared with known prior art techniques.

摘要翻译： 提供了一种结合了用于控制存储器件内的写入操作的技术的存储器件和方法。 存储器件具有存储器单元阵列，每个存储器单元支持该存储器单元的写入和同时读取。 写入电路在写入操作期间被布置为向阵列内的多个寻址的存储器单元提供写入数据，而字线选择电路响应于写入操作的开始，以断言使能寻址的写入字线信号 存储单元存储写数据。 在写入操作期间布置比较电路以将写入数据与当前存储在寻址的存储器单元中的数据进行比较。 在检测到写入数据与当前存储在所寻址的存储器单元中的数据相匹配时，比较电路将一个控制信号置于字线选择电路中，使得字线选择电路解除写入字线信号。 结果，被断言的写入字线信号的脉冲宽度取决于寻址的存储器单元存储写入数据所花费的时间，从而与已知的现有技术技术相比导致脉冲宽度的大小显着降低 。

公开(公告)号：US20120230122A1

公开(公告)日：2012-09-13

申请号：US13064189

申请日：2011-03-09

申请人： Vikas Chandra ,  Daeyeon Kim

发明人： Vikas Chandra ,  Daeyeon Kim

IPC分类号： G11C7/10

CPC分类号： G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  G11C11/418

摘要： A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse width of the asserted write word line signal is dependent on time taken by the addressed memory cells to store the write data, thereby leading to a significant reduction in the size of the pulse width when compared with known prior art techniques.

摘要翻译： 提供了一种结合了用于控制存储器件内的写入操作的技术的存储器件和方法。 存储器件具有存储器单元阵列，每个存储器单元支持该存储器单元的写入和同时读取。 写入电路在写入操作期间被布置为向阵列内的多个寻址的存储器单元提供写入数据，而字线选择电路响应于写入操作的开始，以断言使能寻址的写入字线信号 存储单元存储写数据。 在写入操作期间布置比较电路以将写入数据与当前存储在寻址的存储器单元中的数据进行比较。 在检测到写入数据与当前存储在所寻址的存储器单元中的数据相匹配时，比较电路将一个控制信号置于字线选择电路中，使得字线选择电路解除写入字线信号。 结果，被断言的写入字线信号的脉冲宽度取决于寻址的存储器单元存储写入数据所花费的时间，从而与已知的现有技术技术相比导致脉冲宽度的大小显着降低 。