公开(公告)号：US09104389B2

公开(公告)日：2015-08-11

申请号：US13276085

申请日：2011-10-18

申请人： Vikas Chandra ,  Sarika Sinha

发明人： Vikas Chandra ,  Sarika Sinha

IPC分类号： G06F9/44

CPC分类号： G06F8/24

摘要： Inheritance contributions of programming class functions and class variables are diagrammed. A functional diagram illustrates individual class contributions of functions. A variable composition diagram illustrates individual class contributions of variables. A diagrammatic depiction of functions overridden and functions contributed in the inheritance hierarchy is provided. Functions which are unique, overridden and/or have contributions in different classes of the hierarchy are visually distinguished (e.g., by distinguishing marks). Classes in the hierarchy are graphically depicted with relative sizes based on percent contribution.

摘要翻译： 编程类函数和类变量的继承贡献如图所示。 功能图说明了功能的各个类的贡献。 变量组合图说明了变量的个别类贡献。 提供了覆盖的功能和继承层次中贡献的功能的图示。 在层次结构的不同类别中唯一，覆盖和/或具有贡献的功能在视觉上不同（例如通过区分标记）。 层次结构中的类以图形方式绘制，基于贡献百分比的相对大小。

公开(公告)号：US08493120B2

公开(公告)日：2013-07-23

申请号：US13064207

申请日：2011-03-10

申请人： Mihir Rajanikant Choudhury ,  Vikas Chandra

发明人： Mihir Rajanikant Choudhury ,  Vikas Chandra

IPC分类号： H03K3/00

CPC分类号： G11C11/4125 ,  G11C5/005

摘要： Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. Configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets. Such an approach has minimal area and power consumption overhead, and provides a small storage circuit that can be readily used in a wide variety of sequential cell designs.

摘要翻译： 存储电路具有增加的对单个事件的影响的弹性以及这种电路的操作方法。 存储电路具有以至少一种操作模式配置以执行第一存储功能的第一存储块和以至少一种操作模式配置的第二存储块，以执行与所述第一存储功能不同的第二存储功能。 配置电路响应于第二存储功能未使用的预定操作模式，以将第二存储块配置为与第一存储块并行操作。 通过在其中一个存储块不执行有用功能的情况下并行地布置两个存储块，这实际上增加了仍然执行有用存储功能的存储块的大小，并且因此增加了其对单个事件的弹性 烦恼 这种方法具有最小的面积和功耗开销，并且提供可以容易地用于各种顺序单元设计中的小型存储电路。

公开(公告)号：US08488369B2

公开(公告)日：2013-07-16

申请号：US13064209

申请日：2011-03-10

申请人： Vikas Chandra ,  Robert Campbell Aitken

发明人： Vikas Chandra ,  Robert Campbell Aitken

IPC分类号： G11C11/00

CPC分类号： G11C29/06 ,  G11C11/412

摘要： A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a burn-in process during which one or more operating parameters of the memory device are set to induce aging of the memory cells. During the burn-in process, for each memory cell in the subset, the value stored in that memory cell is fixed to a selected value which exposes that memory cell to a stress condition. In contrast, for each memory cell not in the subset, the value stored in that memory cell is alternated during the burn-in process in order to alleviate exposure of that memory cell to the stress condition. Such an approach allows a tightening of the distribution of the chosen characteristic, thus improving the worst case memory cells.

摘要翻译： 提供一种用于改变形成存储器件的多个存储单元的选定特性的分布的方法。 该方法包括识别所选择特性的值在分布的预定端区域内的存储器单元的子集，然后执行老化过程，在该过程中存储器件的一个或多个操作参数被设置为引发老化 的记忆细胞。 在老化过程中，对于子集中的每个存储器单元，存储在该存储器单元中的值被固定为将该存储器单元暴露于应力条件的选定值。 相比之下，对于不在子集中的每个存储器单元，存储在该存储器单元中的值在老化过程中交替，以便缓解该存储单元暴露于应力条件。 这种方法允许紧缩所选特征的分布，从而改善最坏情况的存储单元。

公开(公告)号：US08363484B2

公开(公告)日：2013-01-29

申请号：US13064189

申请日：2011-03-09

申请人： Vikas Chandra ,  Daeyeon Kim

发明人： Vikas Chandra ,  Daeyeon Kim

IPC分类号： G11C7/10

CPC分类号： G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  G11C11/418

摘要： A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse width of the asserted write word line signal is dependent on time taken by the addressed memory cells to store the write data, thereby leading to a significant reduction in the size of the pulse width when compared with known prior art techniques.

摘要翻译： 提供了一种结合了用于控制存储器件内的写入操作的技术的存储器件和方法。 存储器件具有存储器单元阵列，每个存储器单元支持该存储器单元的写入和同时读取。 写入电路在写入操作期间被布置为向阵列内的多个寻址的存储器单元提供写入数据，而字线选择电路响应于写入操作的开始，以断言使能寻址的写入字线信号 存储单元存储写数据。 在写入操作期间布置比较电路以将写入数据与当前存储在寻址的存储器单元中的数据进行比较。 在检测到写入数据与当前存储在所寻址的存储器单元中的数据相匹配时，比较电路将一个控制信号置于字线选择电路中，使得字线选择电路解除写入字线信号。 结果，被断言的写入字线信号的脉冲宽度取决于寻址的存储器单元存储写入数据所花费的时间，从而与已知的现有技术技术相比导致脉冲宽度的大小显着降低 。

公开(公告)号：US08339876B2

公开(公告)日：2012-12-25

申请号：US12591127

申请日：2009-11-09

申请人： Vikas Chandra ,  Satyanand Vijay Nalam ,  Cezary Pietrzyk ,  Robert Campbell Aitken

发明人： Vikas Chandra ,  Satyanand Vijay Nalam ,  Cezary Pietrzyk ,  Robert Campbell Aitken

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C11/419

摘要： A static random access memory (SRAM) includes a data line for transferring data to and from the memory and at least one reset line, a plurality of storage cells, each cell including an asymmetric feedback loop; an access device for selectively providing a connection between the at data line and the cell's first access node; a reset device for selectively providing a connection between a reset line and the cell's second access node. The SRAM further includes data access control circuitry for generating control signals for independently controlling the access device and the reset device and to generate a data access control signal. The SRAM also generates a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell.

摘要翻译： 静态随机存取存储器（SRAM）包括用于将数据传送到存储器和从存储器传送数据的数据线和至少一个复位线，多个存储单元，每个单元包括非对称反馈回路; 用于选择性地提供所述at数据线和所述小区的第一接入节点之间的连接的接入设备; 复位装置，用于选择性地提供复位线与小区的第二接入节点之间的连接。 SRAM还包括用于产生控制信号的数据访问控制电路，用于独立地控制访问设备和复位设备并产生数据访问控制信号。 SRAM还产生复位控制信号以触发复位装置，以响应于将互补预定值写入存储单元的写请求而在至少一个复位线和第二接入节点之间提供连接。

公开(公告)号：US20120233233A1

公开(公告)日：2012-09-13

申请号：US13064121

申请日：2011-03-07

申请人： Vikas Chandra

发明人： Vikas Chandra

IPC分类号： G06F7/58

CPC分类号： G06F7/588

摘要： An apparatus and method for generating a random number are provided, the apparatus having at least one generator circuit, each generator circuit being configured to provide a first operating mode and a second operating mode, in the first operating mode each generator circuit operating as an oscillator, and in the second operating mode each generator circuit operating as a state retention element. A control signal generator then generates a control signal for input to each generator circuit. Each generator circuit is responsive to the input control signal being at a set level to operate in the first operating mode, and is responsive to the input control signal being at a clear level to operate in the second operating mode. On a transition of the input control signal from the set level to the clear level, each generator circuit is configured to capture within the state retention element a current value of the oscillator, and to output that current value to form at least part of the random number. Such an approach provides a particularly simple, efficient and low area apparatus for generating a random number.

摘要翻译： 提供一种用于产生随机数的装置和方法，所述装置具有至少一个发生器电路，每个发生器电路被配置为在第一操作模式中提供第一操作模式和第二操作模式，每个发生器电路作为振荡器 并且在第二操作模式中，每个发电机电路作为状态保持元件工作。 然后，控制信号发生器产生用于输入到每个发生器电路的控制信号。 每个发电机电路响应于处于设定电平的输入控制信号在第一操作模式下工作，并且响应于输入控制信号处于明确的水平以在第二操作模式下操作。 在输入控制信号从设定电平到清除电平的转变时，每个发生器电路被配置为在状态保持元件内捕获振荡器的电流值，并输出该电流值以形成至少部分随机 数。 这种方法提供了用于产生随机数的特别简单，有效和低区域的装置。

公开(公告)号：US20120230129A1

公开(公告)日：2012-09-13

申请号：US13064209

申请日：2011-03-10

申请人： Vikas Chandra ,  Robert Campbell Aitken

发明人： Vikas Chandra ,  Robert Campbell Aitken

IPC分类号： G11C7/00

CPC分类号： G11C29/06 ,  G11C11/412

摘要： A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a burn-in process during which one or more operating parameters of the memory device are set to induce aging of the memory cells. During the burn-in process, for each memory cell in the subset, the value stored in that memory cell is fixed to a selected value which exposes that memory cell to a stress condition. In contrast, for each memory cell not in the subset, the value stored in that memory cell is alternated during the burn-in process in order to alleviate exposure of that memory cell to the stress condition. Such an approach allows a tightening of the distribution of the chosen characteristic, thus improving the worst case memory cells.

摘要翻译： 提供一种用于改变形成存储器件的多个存储单元的选定特性的分布的方法。 该方法包括识别所选择特性的值在分布的预定端区域内的存储器单元的子集，然后执行老化过程，在该过程中存储器件的一个或多个操作参数被设置为引发老化 的记忆细胞。 在老化过程中，对于子集中的每个存储器单元，存储在该存储器单元中的值被固定为将该存储器单元暴露于应力条件的选定值。 相比之下，对于不在子集中的每个存储器单元，存储在该存储器单元中的值在老化过程中交替，以便缓解该存储单元暴露于应力条件。 这种方法允许紧缩所选特征的分布，从而改善最坏情况的存储单元。

公开(公告)号：US20120230122A1

公开(公告)日：2012-09-13

申请号：US13064189

申请日：2011-03-09

申请人： Vikas Chandra ,  Daeyeon Kim

发明人： Vikas Chandra ,  Daeyeon Kim

IPC分类号： G11C7/10

CPC分类号： G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  G11C11/418

摘要： A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse width of the asserted write word line signal is dependent on time taken by the addressed memory cells to store the write data, thereby leading to a significant reduction in the size of the pulse width when compared with known prior art techniques.

摘要翻译： 提供了一种结合了用于控制存储器件内的写入操作的技术的存储器件和方法。 存储器件具有存储器单元阵列，每个存储器单元支持该存储器单元的写入和同时读取。 写入电路在写入操作期间被布置为向阵列内的多个寻址的存储器单元提供写入数据，而字线选择电路响应于写入操作的开始，以断言使能寻址的写入字线信号 存储单元存储写数据。 在写入操作期间布置比较电路以将写入数据与当前存储在寻址的存储器单元中的数据进行比较。 在检测到写入数据与当前存储在所寻址的存储器单元中的数据相匹配时，比较电路将一个控制信号置于字线选择电路中，使得字线选择电路解除写入字线信号。 结果，被断言的写入字线信号的脉冲宽度取决于寻址的存储器单元存储写入数据所花费的时间，从而与已知的现有技术技术相比导致脉冲宽度的大小显着降低 。

公开(公告)号：US20120229187A1

公开(公告)日：2012-09-13

申请号：US13064207

申请日：2011-03-10

申请人： Mihir Rajanikant Choudhury ,  Vikas Chandra

发明人： Mihir Rajanikant Choudhury ,  Vikas Chandra

IPC分类号： H03K3/289 ,  H03K3/00

CPC分类号： G11C11/4125 ,  G11C5/005

摘要： Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. Configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets. Such an approach has minimal area and power consumption overhead, and provides a small storage circuit that can be readily used in a wide variety of sequential cell designs.

摘要翻译： 存储电路具有增加的对单个事件的影响的弹性以及这种电路的操作方法。 存储电路具有以至少一种操作模式配置以执行第一存储功能的第一存储块和以至少一种操作模式配置的第二存储块，以执行与所述第一存储功能不同的第二存储功能。 配置电路响应于第二存储功能未使用的预定操作模式，以将第二存储块配置为与第一存储块并行操作。 通过在其中一个存储块不执行有用功能的情况下并行地布置两个存储块，这实际上增加了仍然执行有用存储功能的存储块的大小，并且因此增加了其对单个事件的弹性 烦恼 这种方法具有最小的面积和功耗开销，并且提供可以容易地用于各种顺序单元设计中的小型存储电路。

公开(公告)号：US20110261633A1

公开(公告)日：2011-10-27

申请号：US12662533

申请日：2010-04-21

申请人： Vikas Chandra ,  Cezary Pietrzyk ,  Robert Campbell Aitken

发明人： Vikas Chandra ,  Cezary Pietrzyk ,  Robert Campbell Aitken

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/413 ,  G11C2211/4013

摘要： An integrated circuit is provided comprising at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory cells, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line. Read circuitry is coupled to the plurality of bit lines, configured such that in a read operation, in which the at least three memory cells are all coupled to the shared bit line by means of the common word line signal, a read data value is determined in dependence on a voltage of the shared bit line, dependent on data values stored in the at least three memory cells. If, at a time of the read operation, one of the at least three memory cells holds a complement value of the written data value, the voltage of the shared bit line nonetheless has a value such that the read data value is determined with the same value as the written data value.

摘要翻译： 提供了集成电路，其包括具有多行存储器单元和多列位单元的至少一个存储单元阵列。 存储单元的每一列耦合到多个位线中的一个。 存储单元的每行被耦合到多个字线之一，以根据相应的字线信号来控制该行存储单元与多个位线的耦合。 字线驱动器电路被配置为将至少三行存储器单元的字线组合在一起，使得至少三行存储器单元的字线共享公共字线信号。 因此，在写入操作中，将写入存储器单元阵列的写入数据值写入至少三个具有共享位线的存储单元。 读取电路耦合到多个位线，被配置为使得在读取操作中，至少三个存储器单元通过公共字线信号都耦合到共享位线，读取数据值被确定 取决于存储在至少三个存储器单元中的数据值，依赖于共享位线的电压。 如果在读取操作时，至少三个存储器单元中的一个存储器单元保持写入的数据值的补码值，则共享位线的电压仍然具有使得读取的数据值被确定为相同的值 值作为写入数据值。