公开(公告)号：US20110297935A1

公开(公告)日：2011-12-08

申请号：US13201977

申请日：2009-02-23

Applicant: Hubert Bode ,  Andreas Laudenbach ,  Andreas Roth

Inventor： Hubert Bode ,  Andreas Laudenbach ,  Andreas Roth

IPC: H01L23/58

CPC classification number: H01L23/585 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value.

Abstract translation: 半导体器件包括设置有第一类型的掺杂的衬底，电子电路设置在其上，由设置有第二类型的掺杂的衬底的电路部分围绕; 至少一个焊盘，用于将所述电子电路连接到所述衬底外部的外部设备，由被提供有所述第二类型的掺杂的焊盘部分围绕; 感测装置，包括设置有第一类型的掺杂的衬底的传感器部分，用于感测形成衬底的局部电势的度量的参数; 以及评估单元，连接到感测装置，用于基于参数和参考值之间的差异提供评估信号。

公开(公告)号：US20100164569A1

公开(公告)日：2010-07-01

申请号：US12664028

申请日：2007-06-14

Applicant: Hubert Bode ,  Andreas Laudenbach ,  Andreas Roth ,  Engelbert Wittich

Inventor： Hubert Bode ,  Andreas Laudenbach ,  Andreas Roth ,  Engelbert Wittich

IPC: H03L7/06 ,  H03L7/00 ,  H03K5/1252

CPC classification number: H03K5/1252

Abstract: A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.

Abstract translation: 用于检测时钟信号上不想要的信号的电路装置包括用于接收时钟信号的输入端和锁相环PLL电路，其具有耦合到用于接收时钟信号的电路装置的输入端的参考输入端和用于提供时钟信号的输出端 PLL输出信号。 电路装置还包括耦合到PLL电路的输出和电路装置的输入的检测器。 检测器被布置为使用PLL输出信号来识别时钟信号中的正确转换，并且由于来自时钟信号的不期望的信号而去除不正确的转换，以便在电路装置的输出处提供经滤波的时钟信号。