公开(公告)号：US20130181256A1

公开(公告)日：2013-07-18

申请号：US13781786

申请日：2013-03-01

Applicant: Infineon Technologies AG

Inventor： Harald Gossner ,  Ramgopal Rao ,  Angada Sachid ,  Ashish Pal ,  Ram Asra

IPC: H01L29/165

CPC classification number: H01L29/165 ,  H01L21/26586 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/66356 ,  H01L29/7391

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.

Abstract translation: 在一个实施例中，提供了半导体器件。 半导体器件可以包括具有主处理表面的衬底，包括第一导电类型的第一材料的第一源极/漏极区域，包括第二导电类型的第二材料的第二源极/漏极区域，其中第二导电类型 不同于第一导电类型，电耦合在第一源极/漏极区域和第二源极/漏极区域之间的主体区域，其中主体区域在第一方向上比第一源极/漏极区域在第一方向 垂直于基板的主处理表面，设置在主体区域上的栅极电介质和设置在栅极电介质上的栅极区域，其中栅极区域与第一源极/漏极区域的至少一部分重叠， 的身体区域在第一个方向。

公开(公告)号：US20130077197A1

公开(公告)日：2013-03-28

申请号：US13676748

申请日：2012-11-14

Applicant: Infineon Technologies AG

Inventor： Wolfgang Soldner ,  Gernot Langguth ,  Christian Russ ,  Harald Gossner

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L2924/0002 ,  H03K17/08122 ,  H01L2924/00

Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.

Abstract translation: 本公开的实施例涉及静电放电（ESD）保护技术。 例如，一些实施例包括可变电阻器，其选择性地将来自第一电路节点的输入ESD脉冲的功率分流到第二电路节点并远离半导体器件。 提供给可变电阻器的控制电压使得晶体管在只有亚阈值电流（如果有的话）流动的完全关闭模式之间改变; 其中最大量的电流流动的完全启动模式; 以及其中中间和时变量的电流流动的模拟模式。 特别地，模拟模式允许ESD保护装置比先前可实现的更精确地分流功率，使得ESD保护装置可以保护半导体器件免受ESD脉冲。