公开(公告)号：US09449928B2

公开(公告)日：2016-09-20

申请号：US14252804

申请日：2014-04-15

Applicant: Infineon Technologies AG

Inventor： Joachim Hirschler ,  Gudrun Stranzl

IPC: H01L21/302 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/768 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L23/564 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.

Abstract translation: 根据各种实施例的层布置可以包括：晶片; 设置在晶片上的钝化层; 保护层，设置在远离晶片的钝化面的至少一个表面上; 以及掩模层，其设置在所述保护层的远离所述晶片的至少一个表面上，其中所述保护层包括可选择性地蚀刻到所述钝化材料的材料，并且其中所述掩模层包括可选择性地蚀刻的材料 到保护层的材料。