公开(公告)号：US20240355695A1

公开(公告)日：2024-10-24

申请号：US18761906

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Shu WANG

IPC分类号： H01L23/31 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/29 ,  H01L23/535

CPC分类号： H01L23/3171 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/31055 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76895 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/535

摘要： A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.

公开(公告)号：US12125745B2

公开(公告)日：2024-10-22

申请号：US17949325

申请日：2022-09-21

申请人： General Electric Company

发明人： Cheng-Po Chen ,  Reza Ghandi ,  David Richard Esler ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Liang Yin

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

CPC分类号： H01L21/76832 ,  H01L21/02172 ,  H01L23/3192 ,  H01L23/53252 ,  H01L24/05 ,  H01L2224/05599 ,  H01L2924/1904

摘要： An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.

公开(公告)号：US20240347515A1

公开(公告)日：2024-10-17

申请号：US18757531

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L23/291 ,  H01L24/97

摘要： A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.

公开(公告)号：US12113034B2

公开(公告)日：2024-10-08

申请号：US18138865

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chien-Hsuan Liu

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/585 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/5283

摘要： A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

公开(公告)号：US20240321639A1

公开(公告)日：2024-09-26

申请号：US18602230

申请日：2024-03-12

申请人： STMicroelectronics International N.V.

发明人： Carlos Augusto SUAREZ SEGOVIA ,  David PARKER ,  Pierre BAR

IPC分类号： H01L21/78 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/78 ,  H01L21/31116 ,  H01L21/32136 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585

摘要： A wafer includes a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region. A hard mask is formed having a pattern that defines a dicing line. The formation of the hard mask includes a first etching of an opening in the dicing region to expose the semiconductor substrate in the dicing region, a second etching of an opening in the contact region to expose a surface of a metal contact in the contact region, and a chemical treatment for cleaning the uncovered surface of the metal contact. A vertical dielectric layer is deposited to cover edges of the opening defining the dicing line. This layer is deposited before the chemical treatment is performed.

公开(公告)号：US12087757B2

公开(公告)日：2024-09-10

申请号：US18344456

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC分类号： H01L25/04 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L22/14 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182 ,  H01L2924/35

摘要： In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

公开(公告)号：US20240282728A1

公开(公告)日：2024-08-22

申请号：US18652868

申请日：2024-05-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L24/05 ,  H01L23/31 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/02 ,  H01L24/03 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/564 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2924/1033

摘要： An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US20240266406A1

公开(公告)日：2024-08-08

申请号：US18166133

申请日：2023-02-08

申请人： NXP USA, Inc.

发明人： Congyong Zhu ,  Darrell Glenn Hill ,  David Robert Currier

IPC分类号： H01L29/40 ,  H01L23/31 ,  H01L23/48 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/408 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

摘要： A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. When fabricating the transistor device, at least one dielectric layer may be formed over ohmic contact structures of the transistor device, which may mitigate migration of material, such as metal, from the ohmic contact structures onto sensitive surfaces of the transistor device during subsequent fabrication processes. The transistor device may include one or more dielectric spacers, including at least one dielectric spacer disposed at a side wall of a gate channel through which gate structure contacts the substrate. The transistor device may include a field plate formed at least partially over the gate structure, the field plate having one or more stepped portions, which may improve linearity performance of the transistor device.

公开(公告)号：US20240263348A1

公开(公告)日：2024-08-08

申请号：US18106732

申请日：2023-02-07

申请人： Robert Bosch GmbH

发明人： Bo CHENG ,  Mordechai KORNBLUTH ,  Charles TUFFILE ,  Jens BARINGHAUS ,  Christian HUBER

IPC分类号： C30B25/16 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L23/31

CPC分类号： C30B25/16 ,  C30B25/183 ,  C30B29/406 ,  H01L21/022 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L23/3171 ,  H01L23/3192 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02175 ,  H01L23/291

摘要： A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and AlxGa(1-x)N, wherein 0

公开(公告)号：US12057437B2

公开(公告)日：2024-08-06

申请号：US17338660

申请日：2021-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L23/291 ,  H01L24/97

摘要： A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.