公开(公告)号：US09684510B2

公开(公告)日：2017-06-20

申请号：US14981885

申请日：2015-12-28

Applicant: Intel Corporation

Inventor： Igor Ermolaev ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  Jesus Corbal San Adrian ,  Andrey Naraikin

IPC: G06F9/00 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor a data element shuffle and an operation on the shuffled data elements in response to a single data element shuffle and an operation instruction that includes a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode are described.

公开(公告)号：US20160179515A1

公开(公告)日：2016-06-23

申请号：US14581815

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Jesus Corbal San Adrian ,  Robert N. Hanek ,  Warren E. Ferguson ,  Taraneh Bahrami ,  Avi A. Tevet ,  Dennis R. Bradford ,  Michael Ferry ,  Jingwei Zhang

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3861 ,  G06F9/4552 ,  G06F9/45525

Abstract: An apparatus and method for performing a check on inputs to a mathematical instruction and selecting a default sequence efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: an arithmetic logic unit (ALU) to perform a plurality of mathematical operations using one or more source operands; instruction check logic to evaluate the source operands for a current mathematical instruction and to determine, based on the evaluation, whether to execute a default sequence of operations including executing the current mathematical instruction by the ALU or to jump to an alternate sequence of operations adapted to provide a result for the mathematical instruction having particular types of source operands more efficiently than the default sequence of operations.

Abstract translation: 一种用于对数学指令的输入进行检查并选择有效地管理处理器的架构状态的默认序列的装置和方法。 例如，处理器的一个实施例包括：使用一个或多个源操作数执行多个数学运算的算术逻辑单元（ALU）; 指令检查逻辑以评估当前数学指令的源操作数，并且基于评估来确定是否执行默认操作序列，包括由ALU执行当前数学指令或跳转到适于 为具有比默认操作序列更有效的特定类型的源操作数的数学指令提供结果。

公开(公告)号：US20150095623A1

公开(公告)日：2015-04-02

申请号：US14040409

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Igor Ermolaev ,  Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Gautam B. Doshi ,  Rama Kishan V. Malladi ,  Prasenjit Chakraborty

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3887 ,  G06F15/8007 ,  G06F2212/454

Abstract: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.

Abstract translation: 一种处理器，包括用于接收向量索引负载加算术和/或逻辑（A / L）操作加存储指令的解码单元。 该指令是指示要具有多个打包存储器索引的源打包存储器索引操作数。 该指令还用于指示要具有多个压缩数据元素的源打包数据操作数。 处理器还包括与解码单元耦合的执行单元。 执行单元响应于该指令，从与多个打包存储器索引相对应的存储器位置加载多个数据元素，对源打包数据操作数的多个压缩数据元素执行A / L操作， 加载多个数据元素，并将多个结果数据元素存储在与多个打包存储器索引相对应的存储单元中。