公开(公告)号：US09804842B2

公开(公告)日：2017-10-31

申请号：US14581535

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Jesus Corbal San Adrian ,  Dennis R. Bradford ,  Benjamin C. Chaffin ,  Taraneh Bahrami ,  Jonathan C. Hall ,  Thomas B. Maciukenas ,  Roger Gramunt ,  Rohan Sharma

IPC: G06F9/302 ,  G06F9/305 ,  G06F9/312 ,  G06F9/315 ,  G06F15/76 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30072 ,  G06F9/30101 ,  G06F15/8084

Abstract: An apparatus and method for efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: a source mask register to be logically subdivided into at least a first portion to store a usable portion of a mask value and a second portion to store an indication of whether the usable portion of the mask value has been updated; a control register to store an unusable portion of the mask value; architectural state management logic to read the indication to determine whether the mask value has been updated prior to performing a store operation, wherein if the mask value has been updated, then the architectural state management logic is to read the usable portion of the mask value from the first portion of the source mask register and zero out bits of the unusable portion of the mask value to generate a final mask value to be saved to memory, and wherein if the mask value has not been updated, then the architectural state management logic is to concatenate the usable portion of the mask value with the unusable portion of the mask value read from the control register to generate a final mask value to be saved to memory.

公开(公告)号：US20160179515A1

公开(公告)日：2016-06-23

申请号：US14581815

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Jesus Corbal San Adrian ,  Robert N. Hanek ,  Warren E. Ferguson ,  Taraneh Bahrami ,  Avi A. Tevet ,  Dennis R. Bradford ,  Michael Ferry ,  Jingwei Zhang

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3861 ,  G06F9/4552 ,  G06F9/45525

Abstract: An apparatus and method for performing a check on inputs to a mathematical instruction and selecting a default sequence efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: an arithmetic logic unit (ALU) to perform a plurality of mathematical operations using one or more source operands; instruction check logic to evaluate the source operands for a current mathematical instruction and to determine, based on the evaluation, whether to execute a default sequence of operations including executing the current mathematical instruction by the ALU or to jump to an alternate sequence of operations adapted to provide a result for the mathematical instruction having particular types of source operands more efficiently than the default sequence of operations.

Abstract translation: 一种用于对数学指令的输入进行检查并选择有效地管理处理器的架构状态的默认序列的装置和方法。 例如，处理器的一个实施例包括：使用一个或多个源操作数执行多个数学运算的算术逻辑单元（ALU）; 指令检查逻辑以评估当前数学指令的源操作数，并且基于评估来确定是否执行默认操作序列，包括由ALU执行当前数学指令或跳转到适于 为具有比默认操作序列更有效的特定类型的源操作数的数学指令提供结果。

公开(公告)号：US09032232B2

公开(公告)日：2015-05-12

申请号：US13786939

申请日：2013-03-06

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F1/32 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

公开(公告)号：US09696992B2

公开(公告)日：2017-07-04

申请号：US14581815

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Jesus Corbal San Adrian ,  Robert N. Hanek ,  Warren E. Ferguson ,  Taraneh Bahrami ,  Avi A. Tevet ,  Dennis R. Bradford ,  Michael Ferry ,  Jingwei Zhang

IPC: G06F7/38 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3861 ,  G06F9/4552 ,  G06F9/45525

Abstract: An apparatus and method for performing a check on inputs to a mathematical instruction and selecting a default sequence efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: an arithmetic logic unit (ALU) to perform a plurality of mathematical operations using one or more source operands; instruction check logic to evaluate the source operands for a current mathematical instruction and to determine, based on the evaluation, whether to execute a default sequence of operations including executing the current mathematical instruction by the ALU or to jump to an alternate sequence of operations adapted to provide a result for the mathematical instruction having particular types of source operands more efficiently than the default sequence of operations.

公开(公告)号：US08990597B2

公开(公告)日：2015-03-24

申请号：US13891747

申请日：2013-05-10

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F12/08 ,  G06F1/32 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于 定时器值。 处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。 描述和要求保护其他实施例。