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    Method and apparatus for performing a vector bit reversal and crossing
    1.
    发明授权
    Method and apparatus for performing a vector bit reversal and crossing 有权

    公开(公告)号：US10691452B2

    公开(公告)日：2020-06-23

    申请号：US15729566

    申请日：2017-10-10

    Applicant: Intel Corporation

    Inventor： Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mark J. Charney

    IPC: G06F9/30

    Abstract: An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups.

    Method and apparatus for performing a vector bit gather
    3.
    发明授权
    Method and apparatus for performing a vector bit gather 有权

    公开(公告)号：US10296334B2

    公开(公告)日：2019-05-21

    申请号：US14583639

    申请日：2014-12-27

    Applicant: INTEL CORPORATION

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Mark J. Charney ,  Guillem Sole ,  Roger Espasa

    IPC: G06F9/30

    Abstract: Apparatus, method, and system for performing a vector bit gather are describe herein. One embodiment of a processor includes: a first vector register storing one or more source data elements, a second vector register storing one or more control elements, and a vector bit gather logic. Each of the control elements includes a plurality of bit fields, each of which is associated with a plurality of corresponding bit positions in a destination vector register and is to identify a bit from the one or more corresponding source data element to be copied to each of the plurality of corresponding bit positions. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a bit from the source data elements and responsively copy it to each of the plurality of corresponding bit positions in the destination vector register.

    Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions
    7.
    发明授权
    Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions 有权
    矢量索引存储器访问加上算术和/或逻辑运算处理器，方法，系统和指令

    公开(公告)号：US09552205B2

    公开(公告)日：2017-01-24

    申请号：US14040409

    申请日：2013-09-27

    Applicant: Intel Corporation

    Inventor： Igor Ermolaev ,  Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Gautam B. Doshi ,  Rama Kishan V. Malladi ,  Prasenjit Chakraborty

    IPC: G06F15/80 ,  G06F9/302 ,  G06F9/305 ,  G06F9/312 ,  G06F9/315 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3887 ,  G06F15/8007 ,  G06F2212/454

    Abstract: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.

    Abstract translation: 一种处理器，包括用于接收向量索引负载加算术和/或逻辑（A / L）操作加存储指令的解码单元。 该指令是指示要具有多个打包存储器索引的源打包存储器索引操作数。 该指令还用于指示要具有多个压缩数据元素的源打包数据操作数。 处理器还包括与解码单元耦合的执行单元。 执行单元响应于该指令，从与多个打包存储器索引相对应的存储器位置加载多个数据元素，对源打包数据操作数的多个压缩数据元素执行A / L操作， 加载多个数据元素，并将多个结果数据元素存储在与多个打包存储器索引相对应的存储单元中。

    Method and apparatus for performing a vector bit shuffle
    8.
    发明授权
    Method and apparatus for performing a vector bit shuffle 有权

    公开(公告)号：US10296489B2

    公开(公告)日：2019-05-21

    申请号：US14583636

    申请日：2014-12-27

    Applicant: INTEL CORPORATION

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal San Adrian ,  Robert Valentine ,  Mark J. Charney ,  Guillem Sole ,  Roger Espasa

    IPC: G06F15/80 ,  G06F9/30

    Abstract: A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.

    Architectural register replacement for instructions that use multiple architectural registers
    9.
    发明授权
    Architectural register replacement for instructions that use multiple architectural registers 有权

    公开(公告)号：US10255072B2

    公开(公告)日：2019-04-09

    申请号：US15201310

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Mark J. Charney ,  Robert Valentine ,  Milind B. Girkar ,  Ashish Jha ,  Bret L. Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal San Adrian ,  Jason W. Brandt

    IPC: G06F9/30

    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to explicitly specify a first architectural register and is to implicitly indicate at least a second architectural register. The second architectural register is implicitly to be at a higher register number than the first architectural register. The processor also includes an architectural register replacement unit coupled with the decode unit. The architectural register replacement unit is to replace the first architectural register with a third architectural register, and is to replace the second architectural register with a fourth architectural register. The third architectural register is to be at a lower register number than the first architectural register. The fourth architectural register is to be at a lower register number than the second architectural register. Other processors are also disclosed, as are methods and systems.

    Method and apparatus for performing a vector bit reversal and crossing
    10.
    发明授权
    Method and apparatus for performing a vector bit reversal and crossing 有权

    公开(公告)号：US09785437B2

    公开(公告)日：2017-10-10

    申请号：US14581738

    申请日：2014-12-23

    Applicant: INTEL CORPORATION

    Inventor： Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mark J. Charney

    IPC: G06F9/30 ,  G06F15/76

    CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032

    Abstract: An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups.

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