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公开(公告)号：US20150022532A1
公开(公告)日：2015-01-22
申请号：US14482149
申请日：2014-09-10
Applicant: Intel Corporation
Inventor： Franz P. Clarberg , Carl J. Munkberg , Jon N. Hasselgren , Tomas G. Akenine-Moller
CPC classification number: G06T5/002 , G06T11/40 , G06T13/80 , G06T2207/20182
Abstract: Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box overlap test where planes bounding a moving primitive are overlap tested against a screen tile frustum. According to a second test executed after the first test, for primitive edges against tile corners, the second test is a tile corner versus moving edge overlap test. The corners of the screen space tile are tested against a moving triangle edge in two-dimensional homogeneous space.
Abstract translation: 运动模糊光栅化可能涉及对平截头体的每个平面进行第一次测试。 第一个测试是平截头体平面与移动边界框重叠测试，其中界定移动基元的平面与屏幕平截头体重叠测试。 根据在第一次测试之后执行的第二次测试，对于平铺角落的原始边缘，第二个测试是相对于移动边缘重叠测试的瓦片角。 屏幕空间瓦片的角部针对二维均匀空间中的移动三角形边缘进行测试。
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公开(公告)号：US20140132596A1
公开(公告)日：2014-05-15
申请号：US14119977
申请日：2012-05-31
Applicant: INTEL CORPORATION
Inventor： Carl J. Munkberg , Tomas G. Akenine-Moller , Jon N. Hasselgren
IPC: G06T15/00
CPC classification number: G06T15/005 , G02B27/0075 , G06T15/40 , G06T15/503
Abstract: We present a new culling test for rasterization of simultaneous depth of field and motion blur, which efficiently reduces the set of (x, y, u, v, t) samples that need to be coverage tested within a screen space tile. The test finds linear bounds in u, t space and v, t space respectively, using a separating line algorithm. This test is part of the foundation for an efficient 5D rasterizer that extracts coherence in both defocus and motion blur to minimize the number of visibility tests.
Abstract translation: 我们提出了一种用于同时景深和运动模糊的光栅化的新的剔除测试，这有效地减少了需要在屏幕空间瓦片内覆盖测试的（x，y，u，v，t）样本集。 测试使用分离线算法分别在u，t空间和v，t空间中找到线性边界。 该测试是高效5D光栅化器的基础的一部分，其提取散焦和运动模糊中的相干性，以最小化可见性测试的数量。
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公开(公告)号：US10776994B2
公开(公告)日：2020-09-15
申请号：US16233449
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Tomas G. Akenine-Moller , Jon N. Hasselgren , Carl J. Munkberg
Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle relies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.
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公开(公告)号：US10733695B2
公开(公告)日：2020-08-04
申请号：US15267907
申请日：2016-09-16
Applicant: Intel Corporation
Inventor： Magnus Andersson , Jon N. Hasselgren , Tomas G. Akenine-Moller
Abstract: Embodiments described herein enable a hierarchical-Z unit of a graphics processor to be primed using Hi-Z data generated by occlusion culling operations performed on a general purpose processor. One embodiment provides for instructions to cause operations including performing occlusion culling for a scene via the general purpose processor and storing generated hierarchical-Z data. The Hierarchical-Z data generated during the occlusion culling operations can be shared with the graphics processor and used to prime a hierarchical-Z unit of the graphics processor. The at least a portion of the scene can then be rendered using the hierarchical-Z data after priming the hierarchical-Z unit, improving the effectiveness of hierarchical-Z operations of the graphics processor for the scene.
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公开(公告)号：US10380789B2
公开(公告)日：2019-08-13
申请号：US15268500
申请日：2016-09-16
Applicant: Intel Corporation
Inventor： Magnus Andersson , Tomas G. Akenine-Moller , Jon N. Hasselgren
Abstract: An apparatus and method are described for performing an efficient depth prepass. For example, one embodiment of a method comprising: a method comprising: performing a first pass through a specified portion of a graphics pipeline with only depth rendering active; initializing a coarse depth buffer within the specified portion of the graphics pipeline during the first pass, the coarse depth buffer storing depth data at a level of granularity less than that stored in a per-pixel depth buffer, which is not initialized during the first pass; and performing a second pass through the graphics pipeline following the first pass, the second pass utilizing the full graphics pipeline and using values in the coarse depth buffer initialized by the first pass.
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Patent Agency Ranking
公开(公告)号：US10242286B2
公开(公告)日：2019-03-26
申请号：US14668082
申请日：2015-03-25
Applicant: Intel Corporation
Inventor： Jon N. Hasselgren , Magnus Andersson , Robert M. Toth
Abstract: An index is assigned to each entry in the set of possible coverage masks and two functions are generated. One function translates an index to a coverage mask. Also, a sparse function generates an index from a coverage mask. These functions may be realized in hardware and are used during decompression and compression, respectively.
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公开(公告)号：US10045029B2
公开(公告)日：2018-08-07
申请号：US14270435
申请日：2014-05-06
Applicant: Intel Corporation
Inventor： Tomas G. Akenine-Moller , Jon N. Hasselgren , Carl J. Munkberg
IPC: H04N19/136 , H04N19/137 , H04N19/186 , H04N19/50 , G06T9/00 , G06T11/00 , H04N1/41 , H04N19/426 , G06T11/40
Abstract: First, the colors are partitioned within a tile into distinct groups, such that the variation of color within each group is lowered. Second, each group can be encoded in an efficient manner. The algorithm described herein may give a higher compression ratio than previous algorithms, and therefore may further reduce memory bandwidth at a very low increase in computational cost in some embodiments. The algorithm may be added to a system with existing buffer compression algorithms, handling additional tiles that the existing algorithm fails to compress, thereby increasing the overall compression rate.
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公开(公告)号：US09959643B2
公开(公告)日：2018-05-01
申请号：US14926741
申请日：2015-10-29
Applicant: Intel Corporation
Inventor： Jon N. Hasselgren , Tomas G. Akenine-Moller , Carl J. Munkberg , Franz P. Clarberg , Jim K. Nilsson
Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.
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公开(公告)号：US20180082468A1
公开(公告)日：2018-03-22
申请号：US15267968
申请日：2016-09-16
Applicant: Intel Corporation
Inventor： Tomas G. Akenine-Moller , Magnus Andersson , Jon N. Hasselgren , Carl J. Munkberg , Jim K. Nilsson
Abstract: Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimized shadow mapping are described. In an embodiment, a processor performs one or more operations on depth data of an image tile in response to a determination that the depth data includes a minimum depth value inside the image tile and a maximum depth value inside the image tile. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180082467A1
公开(公告)日：2018-03-22
申请号：US15267631
申请日：2016-09-16
Applicant: Intel Corporation
Inventor： Magnus Andersson , Robert M. Toth , Jon N. Hasselgren , Tomas G. Akenine-Moller
CPC classification number: G06T15/405 , G06T15/005 , G06T15/04 , G06T15/40 , G06T2210/62
Abstract: Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimization for texture-dependent discard operations are described. In an embodiment, a processor performs one or more operations (such as HiZ or Hierarchical Stencil test) on depth data of an image tile in response to a determination that texture space bounds of the image tile is fully opaque. The processor performs the one or more operations regardless of whether a discard operation is enabled. Other embodiments are also disclosed and claimed.
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