公开(公告)号：US20190189500A1

公开(公告)日：2019-06-20

申请号：US16284568

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Jasmeet S. CHAWLA ,  Marie KRYSAK ,  Hui Jae YOO ,  Tristan A. TRONIC

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.