公开(公告)号：US20220113781A1

公开(公告)日：2022-04-14

申请号：US17557034

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Jianfang Zhu ,  Ivan Chen ,  Deepak Samuel Kirubakaran ,  Rajshree Chabukswar ,  Richard Winterton ,  Houfei Chen

IPC: G06F1/324

Abstract: Methods and apparatus for bi-directional control of computing unit frequency are disclosed. An example apparatus to control a frequency of a computing unit includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to determine a performance hint from a first register, the performance hint corresponding to a requested performance of the computing unit for executing a thread associated with software, determine power and performance (PnP) statistics pertaining to the thread from a second register, control the frequency of the computing unit based on the performance hint and the PnP statistics, and provide a pressure of the computing unit to the software.

公开(公告)号：US20190041950A1

公开(公告)日：2019-02-07

申请号：US15938268

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Michael W. Chynoweth ,  Rajshree Chabukswar ,  Eliezer Weissmann ,  Jason W. Brandt ,  Alexander Gendler ,  Ahmad Yasin ,  Patrick Konsor ,  Sneha Gohad ,  William Freelove

IPC: G06F1/32 ,  G06F12/1045 ,  G06F11/34

Abstract: In one embodiment, a processor includes one or more cores including a cache memory hierarchy; a performance monitor coupled to the one or more cores, the performance monitor to monitor performance of the one or more cores, the performance monitor to calculate pipeline cost metadata based at least in part on count information associated with the cache memory hierarchy; and a power controller coupled to the performance monitor, the power controller to receive the pipeline cost metadata and determine a low power state for the one or more cores to enter based at least in part on the pipeline cost metadata. Other embodiments are described and claimed.