公开(公告)号：US11966742B2

公开(公告)日：2024-04-23

申请号：US18311810

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Mark Charney ,  Michael Mishaeli ,  Robert Valentine ,  Itai Ravid ,  Jason W. Brandt ,  Gilbert Neiger ,  Baruch Chaikin ,  Efraim Rotem

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/3842

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US11886918B2

公开(公告)日：2024-01-30

申请号：US17717859

申请日：2022-04-11

Applicant: INTEL CORPORATION

Inventor： Ankush Varma ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Krishnakanth Sistla ,  Nilanjan Palit ,  Abhinav Karhu ,  Eugene Gorbatov ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

CPC classification number: G06F9/5027 ,  G06F9/4812 ,  G06F9/4881 ,  G06F9/542 ,  G06F15/8038

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

公开(公告)号：US11543878B2

公开(公告)日：2023-01-03

申请号：US17042804

申请日：2018-05-01

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Eric Dehaemer ,  Alexander Gendler ,  Nadav Shulman ,  Krishnakanth Sistla ,  Nir Rosenzweig ,  Ankush Varma ,  Ariel Szapiro ,  Arye Albahari ,  Ido Melamed ,  Nir Misgav ,  Vivek Garg ,  Nimrod Angel ,  Adwait Purandare ,  Elkana Korem

IPC: G06F1/32 ,  G06F9/4401 ,  G06F1/329 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/48

Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

公开(公告)号：US20220283619A1

公开(公告)日：2022-09-08

申请号：US17824984

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US11435816B2

公开(公告)日：2022-09-06

申请号：US17215104

申请日：2021-03-29

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3228 ,  G06F9/30 ,  G06F1/324

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US11409572B2

公开(公告)日：2022-08-09

申请号：US16586706

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/30 ,  G06F9/448

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

公开(公告)号：US11340687B2

公开(公告)日：2022-05-24

申请号：US17202765

申请日：2021-03-16

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Efraim Rotem ,  Eliezer Weissmann ,  Yoni Aizik ,  Daniel D. Lederman

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3206

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

公开(公告)号：US11093278B2

公开(公告)日：2021-08-17

申请号：US16605539

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Michael Chynoweth ,  Rajshree Chabukswar ,  Eliezer Weissmann ,  Jeremy Shrall

IPC: G06F9/48 ,  G06F1/324 ,  G06F9/32 ,  G06F9/50 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34

Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.

公开(公告)号：US11074191B2

公开(公告)日：2021-07-27

申请号：US15803244

申请日：2017-11-03

Applicant: Intel Corporation

Inventor： Ben-Zion Friedman ,  Jacob Doweck ,  Eliezer Weissmann ,  James B. Crossland ,  Ohad Falik

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/10 ,  G06F12/1036

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

公开(公告)号：US20210200580A1

公开(公告)日：2021-07-01

申请号：US16729370

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Julius Mandelblat ,  Eliezer Weissmann ,  Rajshree A. Chabukswar ,  Michael W. Chynoweth

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/32

Abstract: Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.