公开(公告)号：US20230402318A1

公开(公告)日：2023-12-14

申请号：US17806280

申请日：2022-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Kisik Choi ,  SOMNATH GHOSH ,  Julien Frougier ,  Stuart Sieg ,  Kevin Shawn Petrarca

IPC: H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L21/76816 ,  H01L21/84 ,  H01L21/76829 ,  H01L21/76804 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/124

Abstract: A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.

公开(公告)号：US20230178433A1

公开(公告)日：2023-06-08

申请号：US17545073

申请日：2021-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Stuart Sieg ,  SOMNATH GHOSH ,  Kisik Choi ,  Kevin Shawn Petrarca

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L27/088

Abstract: A semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.

公开(公告)号：US11257681B2

公开(公告)日：2022-02-22

申请号：US16514235

申请日：2019-07-17

Applicant: International Business Machines Corporation

Inventor： Stuart Sieg ,  Daniel James Dechene ,  Eric Miller

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L27/092

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.