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公开(公告)号：US11430731B2
公开(公告)日：2022-08-30
申请号：US16794922
申请日：2020-02-19
Applicant: Infineon Technologies AG
Inventor： Michael Stadler
IPC: H01L23/528 , H01L25/065 , H01L23/00 , H01L23/532
Abstract: A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.
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Patent Agency Ranking
公开(公告)号：US20220238475A1
公开(公告)日：2022-07-28
申请号：US17155241
申请日：2021-01-22
Applicant: Infineon Technologies AG
Inventor： Thomas Stoek , Michael Stadler , Mohd Hasrul Zulkifli
IPC: H01L23/00 , H01L23/495
Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.
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公开(公告)号：US11355429B2
公开(公告)日：2022-06-07
申请号：US16774800
申请日：2020-01-28
Applicant: Infineon Technologies AG
Inventor： Paul Armand Asentista Calo , Tek Keong Gan , Ser Yee Keh , Tien Heng Lem , Fong Lim , Michael Stadler , Mei Qi Tay
IPC: H01L23/48 , H01L23/498 , H01L21/48 , H01L23/00 , H01L21/60
Abstract: An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.
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公开(公告)号：US20200266141A1
公开(公告)日：2020-08-20
申请号：US16794922
申请日：2020-02-19
Applicant: Infineon Technologies AG
Inventor： Michael Stadler
IPC: H01L23/528 , H01L25/065 , H01L23/00 , H01L23/532
Abstract: A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.
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公开(公告)号：US10575384B2
公开(公告)日：2020-02-25
申请号：US15790520
申请日：2017-10-23
Applicant: Infineon Technologies AG
Inventor： Markus Dielacher , Martin Flatscher , Thomas Gigl , Robert Lobnik , Michael Stadler
Abstract: An apparatus, having a transmitted light power/energy monitor configured to monitor transmitted power/energy of light transmitted by a light source, and a controller configured to determine and control a maximum transmit light time based on the transmitted light power/energy and a transmit light power/energy threshold based on time.
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公开(公告)号：US20190124748A1
公开(公告)日：2019-04-25
申请号：US15790520
申请日：2017-10-23
Applicant: Infineon Technologies AG
Inventor： Markus Dielacher , Martin Flatscher , Thomas Gigl , Robert Lobnik , Michael Stadler
Abstract: An apparatus, having a transmitted light power/energy monitor configured to monitor transmitted power/energy of light transmitted by a light source, and a controller configured to determine and control a maximum transmit light time based on the transmitted light power/energy and a transmit light power/energy threshold based on time.
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