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公开(公告)号：US20220262693A1
公开(公告)日：2022-08-18
申请号：US17177703
申请日：2021-02-17
发明人： Oliver Markus Kreiter , Ludwig Busch , Angel Enverga , Mei Fen Hiew , Tian See Hoe , Elvis Keli , Kean Ming Koe , Sanjay Kumar Murugan , Michael Niendorf , Ivan Nikitin , Bernhard Stiller , Thomas Stoek , Ke Yan Tean
IPC分类号： H01L23/31 , H01L23/495 , H01L21/48 , H01L21/56
摘要： A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.
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公开(公告)号：US11101201B2
公开(公告)日：2021-08-24
申请号：US16289972
申请日：2019-03-01
发明人： Thomas Stoek , Dirk Ahlers , Stefan Macheiner
IPC分类号： H01L23/495 , H01L23/42 , H01L23/31
摘要： A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.
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公开(公告)号：US20200279795A1
公开(公告)日：2020-09-03
申请号：US16289972
申请日：2019-03-01
发明人： Thomas Stoek , Dirk Ahlers , Stefan Macheiner
IPC分类号： H01L23/495 , H01L23/31 , H01L23/42
摘要： A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.
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4.发明申请公开(公告)号：US20200185301A1
公开(公告)日：2020-06-11
申请号：US16701251
申请日：2019-12-03
发明人： Thomas Stoek , Michael Stadler
IPC分类号： H01L23/367 , H01L21/56 , H01L21/48 , H01L23/31 , H01L23/373
摘要： A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.
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公开(公告)号：US11901257B2
公开(公告)日：2024-02-13
申请号：US16701251
申请日：2019-12-03
发明人： Thomas Stoek , Michael Stadler
IPC分类号： H01L23/367 , H01L23/495 , H01L21/56 , H01L23/373 , H01L23/31 , H01L21/48 , H01L23/498
CPC分类号： H01L23/3675 , H01L21/4882 , H01L21/565 , H01L23/3107 , H01L23/3736 , H01L23/49568 , H01L23/49861
摘要： A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.
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公开(公告)号：US20220238475A1
公开(公告)日：2022-07-28
申请号：US17155241
申请日：2021-01-22
IPC分类号： H01L23/00 , H01L23/495
摘要： A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.
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公开(公告)号：US11302613B2
公开(公告)日：2022-04-12
申请号：US16924851
申请日：2020-07-09
发明人： Chau Fatt Chiang , Swee Kah Lee , Josef Maerz , Thomas Stoek , Chee Voon Tan
IPC分类号： H01L23/495 , H01L23/31 , H01L21/56 , H01L21/48 , H01L23/18
摘要： A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.
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公开(公告)号：US10651109B2
公开(公告)日：2020-05-12
申请号：US16504692
申请日：2019-07-08
发明人： Syahir Abd Hamid , Jagen Krishnan , Mian Mian Lam , Jayaganasan Narayanasamy , Fabian Schnoy , Thomas Stoek , Christian Stuempfl
IPC分类号： H01L23/373 , H01L23/495 , H01L21/48 , H01L23/367 , H01L21/56 , H01L23/31
摘要： A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating.
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公开(公告)号：US20180277513A1
公开(公告)日：2018-09-27
申请号：US15469112
申请日：2017-03-24
发明人： Stefan Macheiner , Amirul Afiq Hud , Teck Sim Lee , Thomas Stoek , Lee Shuang Wang , Chooi Mei Chong , Wei Hing Tan
IPC分类号： H01L25/065 , H01L23/498 , H01L23/538 , H01L23/057 , H01L25/00
CPC分类号： H01L25/0655 , H01L23/057 , H01L23/49805 , H01L23/49844 , H01L23/5386 , H01L25/50 , H01L29/7827
摘要： In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.
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公开(公告)号：US20220115245A1
公开(公告)日：2022-04-14
申请号：US17492865
申请日：2021-10-04
发明人： Jayaganasan Narayanasamy , Syahir Abd Hamid , Meng How Chong , Michael Reyes Godoy , Chee Ming Lam , Adbul Rahman Mohamed , Sanjay Kumar Murugan , Thomas Stoek
IPC分类号： H01L21/48 , H01L21/56 , H01L23/495 , H01L23/31
摘要： A method for fabricating a power semiconductor package includes: providing a leadframe having a die pad and a frame, wherein the die pad is connected to the frame by at least one tie bar; attaching a semiconductor die to the die pad; laser cutting through the at least one tie bar, thereby forming a cut surface; and after the laser cutting, molding over the die pad and the semiconductor die, wherein the cut surface is completely covered by molding compound.
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