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    Semiconductor Arrangement and Method for Producing a Semiconductor Arrangement
    4.
    发明申请
    Semiconductor Arrangement and Method for Producing a Semiconductor Arrangement 有权

    公开(公告)号：US20220216139A1

    公开(公告)日：2022-07-07

    申请号：US17704672

    申请日：2022-03-25

    Applicant: Infineon Technologies AG

    Inventor： Michael Stadler

    IPC: H01L23/528 ,  H01L25/065 ,  H01L23/00 ,  H01L23/532

    Abstract: A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.

    INTERCONNECT CLIP FOR VERTICALLY STACKED DIE ARRANGEMENT
    5.
    发明申请
    INTERCONNECT CLIP FOR VERTICALLY STACKED DIE ARRANGEMENT 有权

    公开(公告)号：US20250096082A1

    公开(公告)日：2025-03-20

    申请号：US18369443

    申请日：2023-09-18

    Applicant: Infineon Technologies AG

    Inventor： Mei Yih Goh ,  Chee Voon Tan ,  Sung Hoe Yeong ,  Michael Stadler

    IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07

    Abstract: An electrical interconnect clip includes a die interface portion that is adapted for mating in between two vertically stacked semiconductor dies, and a carrier connection portion that is configured to electrically connect the two vertically stacked semiconductor dies with a carrier, wherein the die interface portion comprises a lower mating surface, an upper mating surface opposite from the lower mating surface, and a solder retention feature formed by one or more grooves in the upper mating surface that are spaced apart from the outer edge sides of the electrical interconnect clip and surround a die attach area of the upper mating surface.

    Semiconductor device and method for fabricating a semiconductor device
    8.
    发明授权
    Semiconductor device and method for fabricating a semiconductor device 有权

    公开(公告)号：US11088105B2

    公开(公告)日：2021-08-10

    申请号：US16695866

    申请日：2019-11-26

    Applicant: Infineon Technologies AG

    Inventor： Thomas Bemmerl ,  Chooi Mei Chong ,  Edward Myers ,  Michael Stadler

    IPC: H01L23/00

    Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

    SEMICONDUCTOR DEVICE COMPRISING A RECESS AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING A RECESS AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20200051880A1

    公开(公告)日：2020-02-13

    申请号：US16519706

    申请日：2019-07-23

    Applicant: Infineon Technologies AG

    Inventor： Thomas Bemmerl ,  Michael Stadler

    IPC: H01L23/13 ,  H01L23/00

    Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a die carrier comprising an X-shaped recess on a first surface of the die carrier; a semiconductor die arranged over the first surface of the die carrier and at least partly covering the X-shaped recess; and a coupling agent attaching the semiconductor die to the die carrier, wherein the coupling agent is at least partially arranged in the X-shaped recess. Each of the four arms of the X-shaped recess points towards a corner of the semiconductor die and extends over an outline of the semiconductor die in an orthogonal projection onto the first surface of the die carrier.

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