公开(公告)号：US09673966B2

公开(公告)日：2017-06-06

申请号：US14968616

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Dima Hammad ,  Vadim Levin ,  Amir Laufer ,  Ron Bar-Lev ,  Noam Familia ,  Itamar Levin

IPC: H04L7/00 ,  H04L1/00 ,  H03L7/08 ,  H03L7/093 ,  H03L7/107 ,  H04L1/20 ,  H04L1/24

CPC classification number: H04L7/0054 ,  H03L7/0807 ,  H03L7/093 ,  H03L7/1075 ,  H04L1/00 ,  H04L1/203 ,  H04L1/24 ,  H04L7/0016 ,  H04L7/0062 ,  H04L7/0079

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

公开(公告)号：US20160173300A1

公开(公告)日：2016-06-16

申请号：US14572756

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Amir Laufer ,  Itamar Levin

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L2025/03579

Abstract: Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.

Abstract translation: 描述了一种装置，其包括具有第一DFE抽头路径和非第一DFE抽头路径的判决反馈均衡器（DFE），其中DFE在非第一DFE抽头路径的信号路径中包括可变延迟电路。 在一些实施例中，提供一种装置，包括：一个夏天; 从夏天接收输入的切片机; 第一反馈回路，用于取消第一后视标，所述第一反馈回路通过将所述切片机耦合到所述夏季而形成回路; 以及用于消除第二后置光标的第二反馈回路，所述第二反馈回路通过将所述第一反馈回路的输入耦合到所述加法器来形成回路，其中所述第二反馈回路在其输入处具有可编程延迟。

公开(公告)号：US08989329B2

公开(公告)日：2015-03-24

申请号：US13836383

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Dima Hammad ,  Vadim Levin ,  Amir Laufer ,  Ron Bar-Lev ,  Noam Familia ,  Itamar Levin

IPC: H04L7/00

CPC classification number: H04L7/0054 ,  H03L7/0807 ,  H03L7/093 ,  H03L7/1075 ,  H04L1/00 ,  H04L1/203 ,  H04L1/24 ,  H04L7/0016 ,  H04L7/0062 ,  H04L7/0079

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.